公开(公告)号：US20040055893A1

公开(公告)日：2004-03-25

申请号：US10253240

申请日：2002-09-23

Applicant: Applied Materials, Inc.

Inventor： Dmitry Lubomirsky ,  Michael X. Yang ,  Sheshraj Tulshibagwale ,  Yezdi Dordi ,  Howard E. Grunes ,  Jick M. Yu ,  Fusen Chen

IPC: C25D017/00 ,  C25D005/02

CPC classification number: C25D7/123 ,  C25D17/06 ,  H01L21/2885

Abstract: A method and apparatus for electrochemically plating on a production surface of a substrate are provided. The apparatus generally includes a plating cell having a plating solution reservoir configured to contain a volume of an electrochemical plating solution, and a substrate support member positioned above the plating solution reservoir, the substrate support member being configured to electrically engage a non-production side of a substrate secured thereto. The substrate support member generally includes a substrate support surface having at least one vacuum channel formed therein, a plurality of electrical contact pins extending from the substrate support surface and being positioned to engage a perimeter of the non-production side of the substrate secured thereto, and at least one annular seal positioned on the substrate support surface radially outward of the plurality of electrical contact pins, the at least one annular seal being configured to prevent flow of the electrochemical plating solution to the plurality of electrical contact pins. The plating cell further includes a power supply in electrical communication with an anode positioned in the electrochemical plating solution and the plurality of electrical contact pins.

Abstract translation: 提供了一种用于在基板的生产表面上进行电化学电镀的方法和装置。 该装置通常包括具有电镀液储存器的电镀槽，该电镀液储存器构造为容纳一定量的电化学电镀溶液，以及位于电镀液储存器上方的基板支撑构件，该基板支撑构件被构造成电接合非电解镀层 固定到其上的基板。 衬底支撑构件通常包括具有形成在其中的至少一个真空通道的衬底支撑表面，从衬底支撑表面延伸并定位成接合固定到其上的衬底的非生产侧的周边的多个电接触销， 以及至少一个环形密封件，其定位在所述多个电接触销的径向外侧的所述基板支撑表面上，所述至少一个环形密封件构造成防止所述电化学电镀液流向所述多个电接触销。 电镀单元还包括与位于电化学电镀溶液中的阳极和多个电接触针电连通的电源。

公开(公告)号：US20020102842A1

公开(公告)日：2002-08-01

申请号：US10074938

申请日：2002-02-11

Applicant: Applied Materials, Inc.

Inventor： Roderick Craig Mosley ,  Hong Zhang ,  Fusen Chen ,  Ted Guo ,  Liang-Yun Chen

IPC: H01L021/44 ,  H01L021/4763

CPC classification number: H01L21/76876 ,  C23C14/568 ,  C23C16/54 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879

Abstract: The present invention relates generally to an improved process for providing uniform step coverage on a substrate and planarization of metal layers to form continuous, void-free contacts or vias in sub-half micron applications. In one aspect of the invention, a refractory layer is deposited onto a substrate having high aspect ratio contacts or vias formed thereon. A CVD metal layer is then deposited onto the refractory layer at low temperatures to provide a conformal wetting layer for a PVD metal. Next, a PVD metal is deposited onto the previously formed CVD metal layer at a temperature below that of the melting point temperature of the metal. The resulting CVD/PVD metal layer is substantially void-free. The metallization process is preferably carried out in an integrated processing system that includes both a PVD and CVD processing chamber so that once the substrate is introduced into a vacuum environment, the metallization of the vias and contacts occurs without the formation of an oxide layer over the CVD Al layer.

公开(公告)号：US20040134769A1

公开(公告)日：2004-07-15

申请号：US10428476

申请日：2003-05-01

Applicant: Applied Materials, Inc.

Inventor： Wei D. Wang ,  Anantha K. Subramani ,  Jianming Fu ,  Praburam Gopalraja ,  Jick M. Yu ,  Fusen Chen

IPC: H01L021/44 ,  C23C014/32

CPC classification number: C23C14/046 ,  C23C14/185 ,  C23C14/345 ,  C23C14/3492 ,  C23C14/541 ,  H01L21/2855 ,  H01L21/76844 ,  H01L21/76865 ,  H01L21/76877

Abstract: A two-step method of filling copper into a high-aspect ratio via or dual-damascene structure. The first step sputters at a low temperature of no more than 100null C. and with at least portions of high wafer bias, thereby filling a lower half of the hole. The initial copper sputtering is preferably performed through multiple cycles of low-level and high-level pedestal bias to deposit copper on exposed corners and to sputter resulting overhangs from the corners while depositing deep in the hole. The second step may include either electrochemical plating or sputtering performed at a higher temperature, e.g., at least 200null C. and with lower wafer bias to complete the hole filling. In another aspect of the invention, diffusion promoting gas such as hydrogen is added to the copper sputter plasma.

Abstract translation: 将铜填充到高纵横比或双镶嵌结构的两步法。 第一步在不超过100℃的低温下进行喷射，并且至少部分高晶片偏置，从而填充孔的下半部分。 初始铜溅射优选通过多个低水平和高水平基座偏压的周期进行，以在暴露的拐角上沉积铜，并且在沉积在孔中深处时从角部溅射所得到的突出端。 第二步可以包括在较高温度例如至少200℃进行的电化学电镀或溅射，并且具有较低的晶片偏置以完成孔填充。 在本发明的另一方面，将扩散促进气体如氢气加入到铜溅射等离子体中。

公开(公告)号：US20030194850A1

公开(公告)日：2003-10-16

申请号：US10124095

申请日：2002-04-16

Applicant: Applied Materials, Inc.

Inventor： John S. Lewis ,  Srinivas Gandikota ,  Sivakami Ramanathan ,  Girish Dixit ,  Robin Cheung ,  Fusen Chen

IPC: H01L021/20 ,  H01L021/44

CPC classification number: H01L21/2855 ,  H01L21/76879

Abstract: A method and apparatus is provided for filling apertures formed in a substrate surface by depositing materials that selectively inhibit or limit the formation or growth of subsequent layers used to fill an aperture. In one aspect, a method is provided for processing a substrate including providing a substrate having a field and apertures formed therein, wherein the apertures each have a bottom and sidewalls, depositing a seed layer on the bottom and sidewalls of the apertures, depositing a growth-inhibiting layer on at least one of the field of the substrate or an upper portion of the sidewalls of the apertures, and depositing a conductive layer on the growth-inhibiting layer and the seed layer. Deposition of the growth-inhibiting layer improves fill of the aperture from the bottom of the aperture up to the field of the substrate.

Abstract translation: 提供了一种方法和装置，用于通过沉积选择性地抑制或限制用于填充孔的后续层的形成或生长的材料来填充形成在衬底表面中的孔。 在一个方面，提供了一种用于处理衬底的方法，包括提供具有形成在其中的场和孔的衬底，其中每个孔具有底部和侧壁，在孔的底部和侧壁上沉积种子层，沉积生长 在衬底的场中的至少一个或孔的侧壁的上部中的至少一个上的抑制层，并且在生长抑制层和种子层上沉积导电层。 生长抑制层的沉积改善了孔的填充，从孔的底部到基底的场。

公开(公告)号：US20040266175A1

公开(公告)日：2004-12-30

申请号：US10894774

申请日：2004-07-20

Applicant: Applied Materials, Inc.

Inventor： Fusen Chen ,  Ling Chen ,  Walter Benjamin Glenn ,  Praburam Gopalraja ,  Jianming Fu

IPC: H01L021/4763 ,  H01L021/00 ,  H01L021/44

CPC classification number: H01L21/76844 ,  C23C14/022 ,  C23C14/046 ,  C23C16/34 ,  C23C16/45525 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76871 ,  H01L21/76873

Abstract: In a first aspect, a method is provided that includes (1) forming a first barrier layer over the sidewalls and bottom of a via using atomic layer deposition within an atomic layer deposition (ALD) chamber; (2) removing at least a portion of the first barrier layer from the bottom of the via by sputter etching; and (3) depositing a second barrier layer on the sidewalls and bottom of the via within the ALD chamber. Numerous other embodiments are provided, as are systems, methods and computer program products in accordance with these and other aspects.

公开(公告)号：US20030116427A1

公开(公告)日：2003-06-26

申请号：US10202778

申请日：2002-07-25

Applicant: Applied Materials, Inc.

Inventor： Peijun Ding ,  Zheng Xu ,  Roderick C. Mosely ,  Suraj Rengarajan ,  Nirmalya Maity ,  Daniel A. Carl ,  Barry Chin ,  Paul F. Smith ,  Darryl Angelo ,  Anish Tolia ,  Jianming Fu ,  Fusen Chen ,  Praburam Gopalraja ,  Xianmin Tang ,  John C. Forster

IPC: C23C014/32 ,  C23C014/34

CPC classification number: H01L21/76844 ,  C23C14/046 ,  C23C14/345 ,  C23C14/3457 ,  C23C14/358 ,  H01J37/321 ,  H01J37/3408 ,  H01J2237/3327 ,  H01L21/2855 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76865 ,  H01L21/76868 ,  H01L21/76873 ,  H01L21/76877 ,  H01L2221/1089

Abstract: A magnetron sputter reactor for sputtering deposition materials such as tantalum, tantalum nitride and copper, for example, and its method of use, in which self-ionized plasma (SIP) sputtering and inductively coupled plasma (ICP) sputtering are promoted, either together or alternately, in the same chamber. Also, bottom coverage may be thinned or eliminated by ICP resputtering. SIP is promoted by a small magnetron having poles of unequal magnetic strength and a high power applied to the target during sputtering. ICP is provided by one or more RF coils which inductively couple RF energy into a plasma. The combined SIP-ICP layers can act as a liner or barrier or seed or nucleation layer for hole. In addition, an RF coil may be sputtered to provide protective material during ICP resputtering.

Abstract translation: 用于溅射诸如钽，氮化钽和铜的沉积材料的磁控溅射反应器及其使用方法，其中促进了自离子等离子体（SIP）溅射和电感耦合等离子体（ICP）溅射，其一起或者 交替地，在同一个房间。 此外，底部覆盖可以通过ICP再溅射而变薄或消除。 SIP由在溅射期间施加到靶的不均匀磁强度和高功率的磁极的小磁控管促进。 ICP由一个或多个将RF能量感应耦合到等离子体中的RF线圈提供。 组合的SIP-ICP层可以作为孔的衬垫或屏障或种子或成核层。 此外，可以在ICP溅射期间溅射RF线圈以提供保护材料。

公开(公告)号：US20020084189A1

公开(公告)日：2002-07-04

申请号：US09754499

申请日：2001-01-03

Applicant: Applied Materials, Inc.

Inventor： Hougong Wang ,  Bo Zheng ,  Girish Dixit ,  Fusen Chen

IPC: C25D021/06 ,  C25D021/16 ,  C25D017/00

CPC classification number: C25D21/10 ,  C25D5/003 ,  C25D5/08 ,  C25D5/20 ,  C25D7/123 ,  C25D17/001

Abstract: A method and associated apparatus of electroplating an object and filling small features. The method comprises immersing the plating surface into an electrolyte solution and mechanically enhancing the concentration of metal ions in the electrolyte solution in the features. In one embodiment, the mechanical enhancement comprises mechanically vibrating the plating surface. In another embodiment, the mechanical enhancement comprises mechanically vibrating the electrolyte solution. In a further embodiment, the mechanical enhancement comprises increasing the pressure applied to the electrolyte solution.

Abstract translation: 一种电镀电镀方法和相关装置，并填充小特征。 该方法包括将电镀表面浸入电解质溶液中，并机械地提高电解质溶液中金属离子的浓度。 在一个实施例中，机械增强包括机械振动电镀表面。 在另一个实施例中，机械增强包括机械振动电解质溶液。 在另一个实施方案中，机械增强包括增加施加到电解质溶液上的压力。

公开(公告)号：US20020060363A1

公开(公告)日：2002-05-23

申请号：US10052681

申请日：2002-01-17

Applicant: Applied Materials, Inc.

Inventor： Ming Xi ,  Paul Frederick Smith ,  Ling Chen ,  Michael X. Yang ,  Mei Chang ,  Fusen Chen ,  Christophe Marcadal ,  Jenny C. Lin

IPC: H01L021/4763 ,  H01L021/44

CPC classification number: H01L21/76804 ,  C25D5/02 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a process sequence and related hardware for filling a patterned feature on a substrate with a metal, such as copper. The sequence comprises first forming a reliable barrier layer in the patterned feature to prevent diffusion of the metal into the dielectric layer through which the patterned feature is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the barrier layer at the bottom of the patterned feature, depositing a second barrier layer, and then filling the patterned feature with a metal, such as copper.

Abstract translation: 本发明的实施例提供了用金属（例如铜）在衬底上填充图案化特征的工艺顺序和相关硬件。 序列包括首先在图案化特征中形成可靠的阻挡层，以防止金属扩散到通过其形成图案化特征的电介质层。 一个序列包括在图案化电介质上形成大致共形的阻挡层，在图案化特征的底部蚀刻阻挡层，沉积第二阻挡层，然后用诸如铜的金属填充图案化的特征。

公开(公告)号：US20030161943A1

公开(公告)日：2003-08-28

申请号：US10367214

申请日：2003-02-13

Applicant: Applied Materials, Inc.

Inventor： Liang-Yuh Chen ,  Ted Guo ,  Roderick Craig Mosley ,  Fusen Chen

IPC: B05D005/12 ,  C23C016/00

CPC classification number: H01L21/28562 ,  H01L21/76879

Abstract: The present invention generally provides a metallization process for forming a highly integrated interconnect. More particularly, the present invention provides a dual damascene interconnect module that incorporates selective chemical vapor deposition aluminum (CVD Al) via fill with a metal wire, preferably copper, formed within a barrier layer. The invention provides the advantages of having copper wires with lower resistivity (greater conductivity) and greater electromigration resistance than aluminum, a barrier layer between the copper wire and the surrounding dielectric material, void-free, sub-half micron selective CVD Al via plugs, and a reduced number of process steps to achieve such integration.

公开(公告)号：US20030017695A1

公开(公告)日：2003-01-23

申请号：US10245119

申请日：2002-09-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Fusen Chen ,  Liang-Yuh Chen ,  Roderick Craig Mosely ,  Moshe Eizenberg

IPC: H01L021/4763

CPC classification number: H01L21/76804 ,  C25D5/02 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention provides a process sequence and related hardware for filling a hole with copper. The sequence comprises first forming a reliable barrier layer in the hole to prevent diffusion of the copper into the dielectric layer through which the hole is formed. One sequence comprises forming a generally conformal barrier layer over a patterned dielectric, etching the bottom of the hole, depositing a second barrier, and then filling the hole with copper. An alternative sequence comprises depositing a first barrier layer over a blanket dielectric layer, forming a hole through both the barrier layer and the dielectric layer, depositing a generally conformal second barrier layer in the hole, removing the barrier layer from the bottom of the hole, and selectively filling the hole with copper.