公开(公告)号：US20250121472A1

公开(公告)日：2025-04-17

申请号：US18486094

申请日：2023-10-12

Applicant: Applied Materials, Inc.

Inventor： Liu Jiang ,  Prayudi Lianto ,  Santosh Kumar Rath ,  Nina Bao ,  Muhammad Adli Danish ,  Aniruddh Khanna ,  Pin Gian Gan ,  Mohammad Faizal Bin Aermie Ang ,  Mayu Yamamura ,  Sivapackia Ganapathiappan ,  Daniel Redfield ,  El Mehdi Bazizi ,  Yen-Chu Yang ,  Pang Yen Ong ,  Rajeev Bajaj

IPC: B24B37/26 ,  B24B37/22 ,  B24D18/00

Abstract: Printable resin precursor compositions and polishing articles including printable resin precursors are provided that are particularly suited for polishing substrates utilized in hybrid bonding applications. Methods and articles may include a plurality of first polishing elements, where at least one of the plurality of first polymer layers forms the polishing surface; and one or more second polishing elements, where at least a region of each of the one or more second polishing elements is disposed between at least one of the plurality of first polishing elements and a supporting surface of the polishing pad. One or more first polishing elements have a Shore D hardness of greater than 60, one or more second polishing elements have a Shore D hardness of from about 20 to less than 60, and the polishing article has a total Shore D hardness of greater than or about 50.

公开(公告)号：US12138742B2

公开(公告)日：2024-11-12

申请号：US17176839

申请日：2021-02-16

Applicant: Applied Materials, Inc. ,  NATIONAL UNIVERSITY OF SINGAPORE

Inventor： Prayudi Lianto ,  Guan Huei See ,  Arvind Sundarrajan ,  Andrivo Rusydi ,  Muhammad Avicenna Naradipa

IPC: B24B57/02 ,  G01N21/21

Abstract: Methods and apparatus for processing a substrate are provided herein. For example, a method of processing a substrate using extended spectroscopic ellipsometry (ESE) includes directing a beam from an extended spectroscopic ellipsometer toward a surface of a substrate for determining in-situ ESE data therefrom during substrate processing, measuring a change of phase and amplitude in determined in-situ ESE data, and determining various aspects of the surface of the substrate using simultaneously complex dielectric function, optical conductivity, and electronic correlations from a measured change of phase and amplitude in the in-situ ESE data.

公开(公告)号：US11342256B2

公开(公告)日：2022-05-24

申请号：US16256809

申请日：2019-01-24

Applicant: Applied Materials, Inc.

Inventor： Han-Wen Chen ,  Steven Verhaverbeke ,  Kyuil Cho ,  Prayudi Lianto ,  Guan Huei See ,  Vincent Dicaprio

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: A method for producing an electrical component is disclosed using a molybdenum adhesion layer, connecting a polyimide substrate to a copper seed layer and copper plated attachment.

公开(公告)号：US20210090905A1

公开(公告)日：2021-03-25

申请号：US16579723

申请日：2019-09-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Guan Huei See ,  Prayudi Lianto ,  Yu Gu

IPC: H01L21/56 ,  H01L21/3105

Abstract: Embodiments of methods for processing a semiconductor substrate are described herein. In some embodiments, a method of processing a semiconductor substrate includes removing material from a backside of a reconstituted substrate having a plurality of dies to expose at least one die of the plurality of dies; etching the backside of the reconstituted substrate to remove material from the exposed at least one die; and depositing a first layer of material on the backside of the reconstituted substrate and the exposed at least one die.

公开(公告)号：US10515927B2

公开(公告)日：2019-12-24

申请号：US15634012

申请日：2017-06-27

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi Lianto ,  Guan Huei See ,  Arvind Sundarrajan ,  Ranga Rao Arnepalli ,  Prerna Goradia

IPC: H01L21/48 ,  H01L23/00 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/56

Abstract: A fan-out process using chemical mechanical planarization (CMP) reduces the step-height between a semiconductor die and the surrounding overmolding of a reconstituted wafer. The reconstituted wafer is formed by overmolding a back side of at least one die that is placed with an active side facing down. The reconstituted wafer is then oriented to expose the die and the active side. A polymer layer is then formed over the reconstituted wafer. A CMP process then removes a portion of the polymer layer until a certain thickness above the die surface is obtained, reducing the step-height between the polymer layer on top of the die surface and the polymer layer on the adjacent mold compound surface. The CMP process can also be performed after a subsequent redistribution layer is formed on the reconstituted wafer.

公开(公告)号：US11901225B2

公开(公告)日：2024-02-13

申请号：US17474394

申请日：2021-09-14

Applicant: Applied Materials, Inc.

Inventor： Eric J. Bergman ,  John L. Klocke ,  Marvin L. Bernt ,  Prayudi Lianto

IPC: H01L21/768 ,  H01L21/288 ,  H01L23/532

CPC classification number: H01L21/76874 ,  H01L21/2885 ,  H01L21/76867 ,  H01L23/53228 ,  H01L21/76886

Abstract: Exemplary methods of plating are described. The methods may include contacting a patterned substrate with a plating bath in a plating chamber. The patterned substrate includes at least one metal interconnect with a contact surface that is exposed to the plating bath. The metal interconnect is made of a first metal characterized by a first reduction potential. The methods further include plating a diffusion layer on the contact surface of the metal interconnect. The diffusion layer is made of a second metal characterized by a second reduction potential that is larger than the first reduction potential of the first metal in the metal interconnects. The plating bath also includes one or more ions of the second metal and a grain refining compound that reduces the formation of pinhole defects in the diffusion layer.

公开(公告)号：US11355358B2

公开(公告)日：2022-06-07

申请号：US16579723

申请日：2019-09-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Guan Huei See ,  Prayudi Lianto ,  Yu Gu

IPC: H01L21/56 ,  H01L21/3105

Abstract: Embodiments of methods for processing a semiconductor substrate are described herein. In some embodiments, a method of processing a semiconductor substrate includes removing material from a backside of a reconstituted substrate having a plurality of dies to expose at least one die of the plurality of dies; etching the backside of the reconstituted substrate to remove material from the exposed at least one die; and depositing a first layer of material on the backside of the reconstituted substrate and the exposed at least one die.

公开(公告)号：US11289387B2

公开(公告)日：2022-03-29

申请号：US16944285

申请日：2020-07-31

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi Lianto ,  Sik Hin Chi ,  Shih-Chao Hung ,  Pin Gian Gan ,  Ricardo Fujii Vinluan ,  Gaurav Mehta ,  Ramesh Chidambaram ,  Guan Huei See ,  Arvind Sundarrajan ,  Upendra V. Ummethala ,  Wei Hao Kew ,  Muhammad Adli Danish Bin Abdullah ,  Michael Charles Kutney ,  Mark McTaggart Wylie ,  Amulya Ligorio Athayde ,  Glen T. Mori

IPC: H01L21/768 ,  H01L21/66 ,  H01L21/304 ,  H01L21/306 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/683

Abstract: Methods and apparatus perform backside via reveal processes using a centralized control framework for multiple process tools. In some embodiments, a method for performing a backside via reveal process may include receiving process tool operational parameters from process tools involved in the backside via reveal process by a central controller, receiving sensor metrology data from at least one or more of the process tools involved in the backside via reveal process, and altering the backside reveal process based, at least in part, on the process tool operational parameters and the sensor metrology data by adjusting two or more of the process tools involved in the backside via reveal process. The profile parameters are configured to prevent backside via breakage during a chemical mechanical polishing (CMP) process.

公开(公告)号：US20180308822A1

公开(公告)日：2018-10-25

申请号：US15634012

申请日：2017-06-27

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi Lianto ,  Guan Huei See ,  Arvind Sundarrajan ,  Ranga Rao Arnepalli ,  Prerna Goradia

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/48

Abstract: A fan-out process using chemical mechanical planarization (CMP) reduces the step-height between a semiconductor die and the surrounding overmolding of a reconstituted wafer. The reconstituted wafer is formed by overmolding a back side of at least one die that is placed with an active side facing down. The reconstituted wafer is then oriented to expose the die and the active side. A polymer layer is then formed over the reconstituted wafer. A CMP process then removes a portion of the polymer layer until a certain thickness above the die surface is obtained, reducing the step-height between the polymer layer on top of the die surface and the polymer layer on the adjacent mold compound surface. The CMP process can also be performed after a subsequent redistribution layer is formed on the reconstituted wafer.

公开(公告)号：US09922874B2

公开(公告)日：2018-03-20

申请号：US15200836

申请日：2016-07-01

Applicant: APPLIED MATERIALS, INC.

Inventor： Prayudi Lianto ,  Sam Lee ,  Charles Sharbono ,  Marvin Louis Bernt ,  Guan Huei See ,  Arvind Sundarrajan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76879 ,  H01L21/76804 ,  H01L21/76873 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329

Abstract: A method of processing a semiconductor substrate includes: immersing a substrate in a first bath, wherein the substrate comprises a barrier layer, a conductive seed layer, and a patterned photoresist layer defining an opening; providing a first electric current between the conductive seed layer and a first anode disposed in electrical contact with the first bath to deposit a conductive material within the opening; stripping the patterned photoresist layer; immersing the substrate in a second bath; providing a second electric current that is a reverse of the first electric current between the conductive seed layer plus the conductive material and a second anode disposed in electrical contact with the second bath; etching the conductive seed layer from atop a field region of the barrier layer; and etching the barrier layer from atop a field region of the substrate.