公开(公告)号：US09632411B2

公开(公告)日：2017-04-25

申请号：US14139457

申请日：2013-12-23

Applicant: Applied Materials, Inc.

Inventor： Timothy Michaelson ,  Timothy W. Weidman ,  Barry Lee Chin ,  Majeed Foad ,  Paul Deaton

IPC: G03C5/00 ,  G03F7/00 ,  G03F7/16 ,  G03F7/09 ,  G03F7/20

CPC classification number: G03F7/70716 ,  G03F7/09 ,  G03F7/167 ,  G03F7/2037

Abstract: A photoresist vapor deposition system includes: a vacuum chamber having a heating element and cooled chuck for holding a substrate, the vacuum chamber having a heated inlet; and a vapor deposition system connected to the heated inlet for volatilizing a precursor into the vacuum chamber for condensing a photoresist over the substrate cooled by the cooled chuck. The deposition system creates a semiconductor wafer system that includes: a semiconductor wafer; and a vapor deposited photoresist over the semiconductor wafer. An extreme ultraviolet lithography system requiring the semiconductor wafer system includes: an extreme ultraviolet light source; a mirror for directing light from the extreme ultraviolet light source; a reticle stage for imaging the light from the extreme ultraviolet light source; and a wafer stage for placing a semiconductor wafer with a vapor deposited photoresist.

公开(公告)号：US20160329222A1

公开(公告)日：2016-11-10

申请号：US15216521

申请日：2016-07-21

Applicant: Applied Materials, Inc.

Inventor： Peng Xie ,  Christopher Dennis Bencher ,  Huixiong Dai ,  Timothy Michaelson ,  Subhash Deshmukh

IPC: H01L21/67 ,  H01L21/687 ,  C23C16/455

CPC classification number: H01L21/67069 ,  C23C16/45544 ,  G03F7/36 ,  G03F7/405 ,  H01L21/67167 ,  H01L21/67201 ,  H01L21/68707

Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

Abstract translation: 在一些实施例中，提供了在衬底上形成蚀刻掩模的方法，其包括（1）在衬底上形成抗蚀剂层; （2）将抗蚀剂层的一个或多个区域暴露于能量源，以便改变暴露区域的物理性质和化学性质中的至少一个; （3）对抗蚀剂层进行硬化处理以提高抗蚀剂层相对于抗蚀剂层的第二区域的第一区域的耐蚀刻性，硬化过程包括将抗蚀剂层暴露于原子层内的一个或多个反应性物质 沉积（ALD）室; 和（4）干蚀刻抗蚀剂层以除去一个或多个第二区域并在抗蚀剂层中形成图案。 提供其他实施例。

公开(公告)号：US09354508B2

公开(公告)日：2016-05-31

申请号：US14139307

申请日：2013-12-23

Applicant: Applied Materials, Inc.

Inventor： Cara Beasley ,  Ralf Hofmann ,  Majeed Foad ,  Timothy Michaelson

IPC: G03F1/24 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F7/70958

Abstract: An integrated extreme ultraviolet (EUV) blank production system includes: a vacuum chamber for placing a substrate in a vacuum; a first deposition system for depositing a planarization layer having a planarized top surface over the substrate; and a second deposition system for depositing a multi-layer stack on the planarization layer without removing the substrate from the vacuum. The EUV blank is in an EUV lithography system includes: an extreme ultraviolet light source; a mirror for directing light from the EUV source; a reticle stage for placing a EUV mask blank with a planarization layer; and a wafer stage for placing a wafer. The EUV blank includes: a substrate; a planarization layer to compensate for imperfections related to the surface of the substrate, the planarization layer having a flat top surface; and a multi-layer stack on the planarization layer.

Abstract translation: 集成的极紫外（EUV）空白生产系统包括：用于将基板放置在真空中的真空室; 第一沉积系统，用于沉积在衬底上具有平坦化顶表面的平坦化层; 以及用于在平坦化层上沉积多层堆叠而不从真空中移除基板的第二沉积系统。 EUV空白在EUV光刻系统中包括：极紫外光源; 一个用于指示EUV来源的光的镜子; 用于放置具有平坦化层的EUV掩模空白的掩模版台; 以及用于放置晶片的晶片台。 EUV空白包括：底物; 平坦化层，用于补偿与衬底的表面相关的缺陷，平坦化层具有平坦的顶表面; 以及平坦化层上的多层堆叠。

公开(公告)号：US20150275364A1

公开(公告)日：2015-10-01

申请号：US14666689

申请日：2015-03-24

Applicant: Applied Materials, Inc.

Inventor： David Thompson ,  Huixiong Dai ,  Patrick M. Martin ,  Timothy Michaelson ,  Kadthala R. Narendrnath ,  Robert Jan Visser ,  Jingjing Xu ,  Lin Zhang

IPC: C23C16/455 ,  C23C16/50 ,  C23C16/458

CPC classification number: C23C16/45544 ,  C23C16/45536 ,  C23C16/45551 ,  C23C16/4584 ,  C23C16/56 ,  H01L21/68764 ,  H01L21/68771

Abstract: Provided are apparatus and methods for the sequential deposition and annealing of a film within a single processing chamber. An energy source positioned within the processing chamber in an area isolated from process gases can be used to rapidly form and decompose a film on the substrate without damaging underlying layers due to exceeding the thermal budget of the device being formed.

Abstract translation: 提供了用于在单个处理室内顺序沉积和退火膜的装置和方法。 位于与处理气体隔离的区域内的处理室内的能量源可用于快速地形成和分解衬底上的膜，而不会由于超过正在形成的器件的热量预算而损坏下层。

公开(公告)号：US20140268080A1

公开(公告)日：2014-09-18

申请号：US14139307

申请日：2013-12-23

Applicant: APPLIED MATERIALS, INC.

Inventor： Cara Beasley ,  Ralf Hofmann ,  Majeed Foad ,  Timothy Michaelson

IPC: G03F1/24 ,  G03F7/20

CPC classification number: G03F1/24 ,  G03F7/70958

Abstract: An integrated extreme ultraviolet (EUV) blank production system includes: a vacuum chamber for placing a substrate in a vacuum; a first deposition system for depositing a planarization layer having a planarized top surface over the substrate; and a second deposition system for depositing a multi-layer stack on the planarization layer without removing the substrate from the vacuum. The EUV blank is in an EUV lithography system includes: an extreme ultraviolet light source; a mirror for directing light from the EUV source; a reticle stage for placing a EUV mask blank with a planarization layer; and a wafer stage for placing a wafer. The EUV blank includes: a substrate; a planarization layer to compensate for imperfections related to the surface of the substrate, the planarization layer having a flat top surface; and a multi-layer stack on the planarization layer.

Abstract translation: 集成的极紫外（EUV）空白生产系统包括：用于将基板放置在真空中的真空室; 第一沉积系统，用于沉积在衬底上具有平坦化顶表面的平坦化层; 以及用于在平坦化层上沉积多层堆叠而不从真空中移除基板的第二沉积系统。 EUV空白在EUV光刻系统中包括：极紫外光源; 一个用于指示EUV来源的光的镜子; 用于放置具有平坦化层的EUV掩模空白的掩模版台; 以及用于放置晶片的晶片台。 EUV空白包括：底物; 平坦化层，用于补偿与衬底的表面相关的缺陷，平坦化层具有平坦的顶表面; 以及平坦化层上的多层堆叠。

公开(公告)号：US20140263172A1

公开(公告)日：2014-09-18

申请号：US14205324

申请日：2014-03-11

Applicant: Applied Materials, Inc.

Inventor： Peng Xie ,  Christopher Dennis Bencher ,  Huixiong Dai ,  Timothy Michaelson ,  Subhash Deshmukh

IPC: G03F7/36

CPC classification number: H01L21/67069 ,  C23C16/45544 ,  G03F7/36 ,  G03F7/405 ,  H01L21/67167 ,  H01L21/67201 ,  H01L21/68707

Abstract: In some embodiments, a method of forming an etch mask on a substrate is provided that includes (1) forming a resist layer on a substrate; (2) exposing one or more regions of the resist layer to an energy source so as to alter at least one of a physical property and a chemical property of the exposed regions; (3) performing a hardening process on the resist layer to increase the etch resistance of first regions of the resist layer relative to second regions of the resist layer, the hardening process including exposing the resist layer to one or more reactive species within an atomic layer deposition (ALD) chamber; and (4) dry etching the resist layer to remove the one or more second regions and to form a pattern in the resist layer. Other embodiments are provided.

Abstract translation: 在一些实施例中，提供了在衬底上形成蚀刻掩模的方法，其包括（1）在衬底上形成抗蚀剂层; （2）将抗蚀剂层的一个或多个区域暴露于能量源，以便改变暴露区域的物理性质和化学性质中的至少一个; （3）对抗蚀剂层进行硬化处理以提高抗蚀剂层相对于抗蚀剂层的第二区域的第一区域的耐蚀刻性，硬化过程包括将抗蚀剂层暴露于原子层内的一个或多个反应性物质 沉积（ALD）室; 和（4）干蚀刻抗蚀剂层以除去一个或多个第二区域并在抗蚀剂层中形成图案。 提供其他实施例。