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公开(公告)号:US5724727A
公开(公告)日:1998-03-10
申请号:US689571
申请日:1996-08-12
Applicant: Mona A. Chopra , Everitt W. Mace , Brian D. Young
Inventor: Mona A. Chopra , Everitt W. Mace , Brian D. Young
CPC classification number: H05K3/4664 , H01L21/4846 , H01L21/4867 , H05K3/102 , H05K2203/107 , Y10T29/4913 , Y10T29/49155
Abstract: An electronic component (15) such as a printed circuit board (PCB) is formed using a sintering process. A layer of dielectric powder (11) is partially converted to a solid layer of dielectric material (14) by exposing selective portions of the powder (11) to a laser (17). A layer of conductive powder (20) is then formed over the solid layer of dielectric material (14) and selectively sintered to form a solid layer of conductive material (19). This process can be used to form an interconnect structure (45), a coaxial structure (60), a cavity (89), a trench structure (90), or a slug (91), conductive traces (19), bond pads (31), or any other circuit board structure.
Abstract translation: 使用烧结工艺形成诸如印刷电路板(PCB)的电子部件(15)。 通过将粉末(11)的选择性部分暴露于激光器(17),电介质粉末(11)的一部分被部分地转换成电介质材料(14)的固体层。 然后在电介质材料(14)的固体层上形成一层导电粉末(20),并选择性地烧结以形成导电材料(19)的固体层。 该工艺可以用于形成互连结构(45),同轴结构(60),空腔(89),沟槽结构(90)或块状物(91),导电迹线(19),接合焊盘 31)或任何其他电路板结构。
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公开(公告)号:US09377504B2
公开(公告)日:2016-06-28
申请号:US14227225
申请日:2014-03-27
Applicant: Stanley A. Cejka , Steven A. Atherton , William J. Downey , James C. Golab , Brian D. Young
Inventor: Stanley A. Cejka , Steven A. Atherton , William J. Downey , James C. Golab , Brian D. Young
IPC: H01L23/52 , G01R31/28 , H01L23/00 , H01L23/498
CPC classification number: G01R31/2818 , G01R31/2812 , G01R31/2882 , G01R31/2896 , H01L22/34 , H01L23/49816 , H01L23/562 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/131 , H01L2224/13111 , H01L2224/13144 , H01L2224/1319 , H01L2224/14179 , H01L2224/16227 , H01L2224/45014 , H01L2224/48227 , H01L2224/4847 , H01L2224/852 , H01L2224/85205 , H01L2924/00014 , H01L2924/30101 , H01L2924/351 , H05K1/141 , H05K3/3436 , H01L2924/014 , H01L2224/45099 , H01L2924/01082 , H01L2924/01047 , H01L2924/01029 , H01L2924/0781 , H01L2924/00012
Abstract: A circuit device mounted on a substrate includes a detection circuit that monitors a characteristic of a return signal to determine an integrity of various interconnects of the device.
Abstract translation: 安装在基板上的电路装置包括检测电路,其检测返回信号的特性,以确定装置的各种互连的完整性。
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公开(公告)号:US08872338B2
公开(公告)日:2014-10-28
申请号:US13675008
申请日:2012-11-13
Applicant: Brian D. Young
Inventor: Brian D. Young
IPC: H01L23/48 , H01L21/768
CPC classification number: H01L23/49822 , H01L23/49816 , H01L23/49838 , H01L2224/16225 , H01L2924/15311
Abstract: A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.
Abstract translation: 半导体器件包括配置有多个导电迹线的衬底。 迹线被配置为电耦合到集成电路(IC)管芯,并且多个导电迹线中的至少一个导电迹线包括在衬底的第一导电层中的第一导电部分,第二导电层中的第二导电部分 以及第一导电部分和第二导电部分之间的第一导电连接。 第一和第二导电部分和第一导电连接件沿至少一个导电迹线的至少一部分形成连续路径。 沿着至少一个导电迹线传导信号的时间延迟在沿多个导电迹线中的另一个传导信号的指定时间延迟时间内。
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公开(公告)号:US5657033A
公开(公告)日:1997-08-12
申请号:US482335
申请日:1995-06-07
Applicant: Brian D. Young
Inventor: Brian D. Young
CPC classification number: H01Q13/02 , H01Q13/085 , H01Q21/30
Abstract: A microwave horn antenna structure including a plurality of planar dielectric insulating layers stacked in laminar fashion so as to have a bottom layer and a top layer, respective similarly shaped conductive trace loops co-axially disposed on a plurality of contiguous ones of the insulating layers and of incrementally increasing size from a lowermost conductive trace loop an uppermost conductive trace loop, and a plurality of conductive vias extending through the planar dielectric layers for electrically interconnecting the respective conductive trace loops. Also disclosed is a flared notch antenna that includes a plurality of planar dielectric insulating layers stacked in laminar fashion, a slanted column of electrically interconnected conductive vias formed in a plurality of contiguous ones of the dielectric insulating layers and a second slanted column of electrically interconnected conductive vias formed in the contiguous ones of the dielectric insulating layers.
Abstract translation: 一种微波喇叭天线结构,包括以层叠的方式层叠以形成底层和顶层的多个平面介电绝缘层,各自相似形状的导电迹线环同轴地设置在多个相邻绝缘层上,以及 从最下面的导电迹线环最上面的导电迹线环逐渐增大的尺寸,以及延伸穿过平面电介质层的多个导电通孔,用于电连接相应的导电迹线环。 还公开了一种扩口切口天线,其包括以层叠方式堆叠的多个平面介质绝缘层,形成在多个相邻的介电绝缘层中的电互连导电通孔的倾斜柱和电互连导电的第二倾斜柱 形成在相邻的介电绝缘层中的通孔。
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公开(公告)号:US5453750A
公开(公告)日:1995-09-26
申请号:US173438
申请日:1993-12-23
Applicant: Daniel M. Battista , Clifton Quan , Keith Whaley , Bruce F. Wolfe , Brian D. Young
Inventor: Daniel M. Battista , Clifton Quan , Keith Whaley , Bruce F. Wolfe , Brian D. Young
CPC classification number: H01P1/047
Abstract: A multistage transmission line interconnect device (50) for joining two microstrip circuits (82, 86). A center conductor pin (52) extends through a cylindrical dielectric (54) to form a coaxial midsection of the device. The ends of the pin extend from the dielectric to form a conductor for a straight open troughline at each end of the device. The ends of the pin are connected to the microstrip circuits by ribbon bonds (80, 84). Because the midsection of the device is coaxial, the microstrip circuits (82, 86) may be oriented at arbitrary angles with respect to one another.
Abstract translation: 一种用于连接两个微带电路(82,86)的多级传输线互连装置(50)。 中心导体销(52)延伸穿过圆柱形电介质(54)以形成该装置的同轴中心部分。 销的端部从电介质延伸以在器件的每个端部处形成用于直的开放波谷的导体。 引脚的端部通过带状键(80,84)连接到微带电路。 因为装置的中部是同轴的,微带电路(82,86)可以相对于彼此以任意角度定向。
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公开(公告)号:US5429859A
公开(公告)日:1995-07-04
申请号:US248276
申请日:1994-05-24
Applicant: Brian D. Young
Inventor: Brian D. Young
IPC: H01L23/544 , H05K1/03 , H05K3/46 , B32B9/00
CPC classification number: H01L23/544 , H01L2223/54426 , H01L2223/54473 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K3/4629 , H05K3/4638 , Y10S428/901 , Y10T428/24777 , Y10T428/24917 , Y10T428/24926
Abstract: A unitized multilayer circuit structure including a plurality of planar dielectric insulating layers stacked in laminar fashion to form a substrate having sides, and at least one alignment groove formed in one side of the substrate.
Abstract translation: 一种单元化多层电路结构,包括以层叠形式堆叠形成具有侧面的基板的多个平面介电绝缘层和形成在所述基板的一侧中的至少一个对准槽。
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