公开(公告)号：US06965163B2

公开(公告)日：2005-11-15

申请号：US10916022

申请日：2004-08-10

Applicant: Chia-Pin Chiu

Inventor： Chia-Pin Chiu

IPC: H01L21/56 ,  H01L23/36 ,  H01L23/427 ,  H01L25/065 ,  H01L23/34

CPC classification number: H01L21/563 ,  H01L23/36 ,  H01L23/427 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05568 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399 ,  H01L2924/00012 ,  H01L2224/05099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A microelectronic die assembly including a heat dissipation device serving as a support structure for the assembly is described. A first microelectronic die is attached by a back surface to a first surface of the heat dissipation device. A first plurality of interconnects are disposed on an active surface of the first microelectronic die. A second microelectronic die is attached by a back surface to the first microelectronic die active surface. A second plurality of interconnects are disposed on an active surface of the second microelectronic die. Any appropriate number of microelectronic dice may be stacked in a like fashion.

公开(公告)号：US20050196904A1

公开(公告)日：2005-09-08

申请号：US10794129

申请日：2004-03-05

Applicant: Anandaroop Bhattacharya ,  Chia-Pin Chiu

Inventor： Anandaroop Bhattacharya ,  Chia-Pin Chiu

IPC: H01L21/48 ,  H01L23/12

CPC classification number: G06F1/20 ,  H05K7/20163

Abstract: Adjacent integrated circuit chips in processor-based systems may be covered with a metal foil cover. The cover may make air flow over the chips more aerodynamic, improving thermal heat transfer and cooling. This may improve performance and reduce power consumption, all without significantly increasing the size of the components.

Abstract translation: 基于处理器的系统中的相邻集成电路芯片可以覆盖有金属箔盖。 盖可以使空气流过芯片更加空气动力学，改善热传递和冷却。 这可以提高性能并降低功耗，而不会显着增加组件的大小。

公开(公告)号：US06315038B1

公开(公告)日：2001-11-13

申请号：US09158227

申请日：1998-09-22

Applicant: Chia-Pin Chiu

Inventor： Chia-Pin Chiu

IPC: F28D702

CPC classification number: H01L23/433 ,  H01L23/3737 ,  H01L2224/73253

Abstract: A method of providing thermal connection between a thermal cooling device and an integrated circuit package is provided. An adhesive is applied to a thermal interface outside a heat transfer area thereof. The thermal interface is attached to the cooling device. The device to be cooled is attached to the thermal interface.

Abstract translation: 提供了一种在热冷却装置和集成电路封装之间提供热连接的方法。 将粘合剂施加到其传热区域外的热界面。 热接口连接到冷却装置。 要冷却的装置连接到热接口。

公开(公告)号：US6121680A

公开(公告)日：2000-09-19

申请号：US251379

申请日：1999-02-16

Applicant: Chia-Pin Chiu ,  Nadir Sharaf ,  Gary Solbrekken ,  Correy D. Cooks

Inventor： Chia-Pin Chiu ,  Nadir Sharaf ,  Gary Solbrekken ,  Correy D. Cooks

IPC: H01L23/42 ,  H01L23/427 ,  H01L23/34

CPC classification number: H01L23/42 ,  H01L23/427 ,  H01L2224/16 ,  H01L2224/29076 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/3011

Abstract: An embodiment of the invention includes an integrated circuit package having a substrate, an integrated circuit mounted to the substrate, a thermal element, and a heat pipe disposed between the integrated circuit and the thermal element. The heat pipe includes a retaining structure impregnated with a thermal grease. The heat pipe is a result of a process that includes the step of impregnating the retaining structure with a thermal grease prior to disposing the heat pipe between the integrated circuit and the thermal element.

Abstract translation: 本发明的实施例包括具有基板，安装到基板的集成电路，热元件和设置在集成电路和热元件之间的热管的集成电路封装。 热管包括浸渍有导热油脂的保持结构。 热管是包括在将热管设置在集成电路和热元件之前用导热油脂浸渍保持结构的工序的结果。

公开(公告)号：US08872349B2

公开(公告)日：2014-10-28

申请号：US13610780

申请日：2012-09-11

Applicant: Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

Inventor： Chia-Pin Chiu ,  Zhiguo Qian ,  Mathew J. Manusharow

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L23/5385 ,  H01L21/02164 ,  H01L21/30604 ,  H01L21/486 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/4821 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及可嵌入封装组件中的桥互连组件的技术和配置。 在一个实施例中，包装组件包括被配置为在第一管芯和第二管芯之间布置电信号的封装衬底和嵌入在封装衬底中并被配置为在第一管芯和第二管芯之间布置电信号的桥， 包括桥接基板，通过桥接基板形成的一个或多个通孔通孔（THV）和布置在桥接基板的表面上的一个或多个走线，以在第一管芯和第二管芯之间布置电信号。 包括迹线和桥互连组件的接地平面的布线特征可以由气隙分开。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140091474A1

公开(公告)日：2014-04-03

申请号：US13630297

申请日：2012-09-28

Applicant: Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L21/50 ,  H01L23/522 ,  H05K7/00

CPC classification number: H01L23/5226 ,  H01L21/563 ,  H01L23/5385 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/00014 ,  H01L2924/206 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

Abstract translation: 本文通常描述用于局部高密度衬底布线的系统和方法的实施例。 在一个或多个实施例中，一种装置包括介质，第一和第二电路元件，互连元件和电介质层。 该介质可以包括其中的低密度路由。 互连元件可以嵌入在介质中，并且可以在其中包括多个导电构件，导电构件可以电耦合到第一电路元件和第二电路元件。 互连元件可以包括其中的高密度路由。 电介质层可以在互连裸片上方，电介质层包括通过其中的第一和第二电路元件。

公开(公告)号：US20140091445A1

公开(公告)日：2014-04-03

申请号：US13631205

申请日：2012-09-28

Applicant: Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

Inventor： Weng Hong Teh ,  Deepak Kulkarni ,  Chia-Pin Chiu ,  Tannaz Harirchian ,  John S. Guzek

IPC: H01L23/34 ,  H01L21/98 ,  H01L23/495

CPC classification number: H01L24/20 ,  H01L21/56 ,  H01L23/34 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/211 ,  H01L2224/32245 ,  H01L2224/73203 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/00

Abstract: An example includes a die package including a microelectronic die having a lower die surface, an upper die surface parallel to the lower die surface, and a die side, the microelectronic die including an active region and an inactive region. The example optionally includes a heat spreader having a lower heat spreader surface, an upper heat spreader surface parallel to the lower heat spreader surface, and at least one heat spreader side, the heat spreader disposed on the upper surface of the microelectronic die in thermal communication with the inactive region of the die and electrically insulated from the active region. The example optionally includes an encapsulation material encapsulating the die side and the heat spreader side and lower heat spreader surface, the encapsulation material including a lower surface substantially parallel to the die lower surface and an upper surface substantially parallel to the die upper surface.

Abstract translation: 一个实例包括包括具有下模表面的微电子管芯，平行于下模表面的上模表面和管芯侧的管芯封装，该微电子管芯包括有源区和非活性区。 该实施例可选地包括具有较低散热器表面的散热器，平行于下部散热器表面的上部散热器表面和至少一个散热器侧，散热器布置在热电连接的微电子管芯的上表面上 具有裸片的非活性区域并与活性区电绝缘。 该实施例可选地包括封装模具侧和散热器侧和下部散热器表面的封装材料，该封装材料包括基本上平行于模具下表面的下表面和基本上平行于模具上表面的上表面。

公开(公告)号：US20120261838A1

公开(公告)日：2012-10-18

申请号：US13531827

申请日：2012-06-25

Applicant: Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

Inventor： Henning Braunisch ,  Chia-Pin Chiu ,  Aleksandar Aleksov ,  Hinmeng Au ,  Stefanie M. Lotz ,  Johanna M. Swan ,  Sujit Sharan

IPC: H01L25/07 ,  H01L21/60 ,  H01L23/538

CPC classification number: H01L23/5385 ,  H01L21/6835 ,  H01L23/13 ,  H01L24/14 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/81001 ,  H01L2224/81005 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1461 ,  H01L2924/15153 ,  H01L2924/19107 ,  H01L2924/351 ,  H01L2924/00

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

Abstract translation: 多芯片封装包括具有第一侧面（111），相对的第二侧面（112）和从第一侧向第二侧延伸的第三侧面（213）的基板（110），第一模具（120） ）和附接到所述基板的第一侧的第二模具（130），以及邻近所述基板的第三侧并连接到所述第一模具和所述第二模具的桥接件（140） 。 基板的任何部分都不在桥下。 该桥在第一管芯和第二管芯之间形成连接。 或者，桥可以设置在衬底中的空腔（615,915）中，或者设置在衬底和裸片层（750）之间。 该桥可以构成一个有源管芯，并且可以使用引线键连接到衬底（241,841,1141,1541）。

公开(公告)号：US07755186B2

公开(公告)日：2010-07-13

申请号：US12006263

申请日：2007-12-31

Applicant: Chia-Pin Chiu ,  Ioan Sauciuc

Inventor： Chia-Pin Chiu ,  Ioan Sauciuc

IPC: H01L23/34

CPC classification number: H01L23/473 ,  H01L23/3675 ,  H01L2224/16225 ,  H01L2224/73253

Abstract: Systems for cooling the backside of a semiconductor die located in a die-down integrated circuit (IC) package are described. The IC package is attached to the topside of a printed circuit board (PCB) with the backside of the die residing below the topside surface of the PCB. A cooling plate is attached to the backside of the die and thermally connected to a heat sink located above the topside surface of the PCB via conduits that pass through openings in the PCB.

Abstract translation: 描述了用于冷却位于降压集成电路（IC）封装中的半导体管芯的背面的系统。 IC封装被连接到印刷电路板（PCB）的顶侧，芯片的背面位于PCB的顶侧表面下方。 冷却板附接到模具的背面，并且通过穿过PCB中的开口的导管热连接到位于PCB的顶侧表面上方的散热器。

公开(公告)号：US20090317986A1

公开(公告)日：2009-12-24

申请号：US12456211

申请日：2009-06-12

Applicant: Chia-Pin Chiu

Inventor： Chia-Pin Chiu

IPC: H01R12/00

CPC classification number: H01R13/2407 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01R13/2442 ,  H05K3/326 ,  H05K3/4015 ,  H05K2201/0311 ,  H05K2201/1031 ,  H05K2201/10719 ,  Y02P70/611 ,  Y10T29/49204 ,  Y10T29/49218 ,  Y10T29/49222

Abstract: The disclosed embodiments relate to the formation of an electrical contact using a skiving technique. The electrical contact includes a spring structure that has been skived away from an underlying metal body, but the spring remains coupled with the metal body which provides a base for the spring structure. The skived spring portion of the electrical contact may comprise a cantilever-like spring, a coil-like spring, or any other suitable type of spring. Such a spring contact may be used to form an electrical connection between an integrated circuit device and a circuit board (or other substrate). Other embodiments are described and claimed.