公开(公告)号：US20050133893A1

公开(公告)日：2005-06-23

申请号：US11051061

申请日：2005-02-04

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/60 ,  H01L23/495 ,  H01L21/48 ,  H01L23/10

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

公开(公告)号：US06891256B2

公开(公告)日：2005-05-10

申请号：US10271654

申请日：2002-10-15

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/50 ,  H01L23/28 ,  H01L23/10 ,  H01L23/34 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract translation: 本发明的实施例涉及半导体管芯封装。 本发明的一个实施例涉及一种半导体管芯封装，其包括：（a）包括第一表面和第二表面的半导体管芯，（b）源极引线结构，其包括具有主表面的突出区域，所述源极引线结构被耦合 （c）栅极引线结构，其耦合到所述第一表面，以及（d）围绕所述源极引线结构和所述半导体管芯的模制材料，其中所述模制材料暴露所述半导体管芯的所述第二表面，以及 源极引线结构的主表面。

公开(公告)号：US06683375B2

公开(公告)日：2004-01-27

申请号：US09881787

申请日：2001-06-15

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L2348

CPC classification number: H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/03442 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05559 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/05647 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2224/05124 ,  H01L2924/00014 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2924/013

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract translation: 公开了一种处理半导体衬底的方法。 该方法包括在具有导电区域的半导体衬底上提供具有孔的掩模。 掩模中的孔设置在导电区上。 将预先形成的导电柱放置在孔中并结合到导电区。

公开(公告)号：US08664752B2

公开(公告)日：2014-03-04

申请号：US13430347

申请日：2012-03-26

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

IPC: H01L23/495

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US20070072347A1

公开(公告)日：2007-03-29

申请号：US11560935

申请日：2006-11-17

Applicant: Jonathan Noquil ,  Seung Choi ,  Rajeev Joshi ,  Chung-Lin Wu

Inventor： Jonathan Noquil ,  Seung Choi ,  Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/00

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract translation: 多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。 组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。 线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。 在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。

公开(公告)号：US20050176233A1

公开(公告)日：2005-08-11

申请号：US10618113

申请日：2003-07-11

Applicant: Rajeev Joshi ,  Chung- Lin Wu ,  Sang-Do Lee ,  Yoon-Hwa Choi

Inventor： Rajeev Joshi ,  Chung- Lin Wu ,  Sang-Do Lee ,  Yoon-Hwa Choi

IPC: H01L23/31 ,  H01L23/485 ,  H01L23/48

CPC classification number: H01L24/10 ,  H01L23/3114 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/01023 ,  H01L2924/013

Abstract: A packaged semiconductor device (a wafer-level chip scale package) containing no UBM between a chip pad and an RDL pattern is described. As well, the device contains only a single non-polymeric insulation layer between the RDL pattern and the solder bump. The single non-polymeric insulation layer does not need high temperature curing processes and so does not induce thermal stresses into the device. As well, manufacturing costs are diminished by eliminating the UBM between the chip pad and the RDL pattern.

Abstract translation: 描述了在芯片焊盘和RDL图案之间不包含UBM的封装半导体器件（晶片级芯片级封装）。 同样，该器件在RDL图案和焊料凸块之间仅包含单个非聚合物绝缘层。 单个非聚合物绝缘层不需要高温固化过程，因此不会对器件引起热应力。 此外，通过消除芯片焊盘和RDL模式之间的UBM，制造成本也降低了。

公开(公告)号：US20050127483A1

公开(公告)日：2005-06-16

申请号：US11048314

申请日：2005-01-31

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/495 ,  H01L23/50 ,  H01L21/48

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

公开(公告)号：US06867481B2

公开(公告)日：2005-03-15

申请号：US10411688

申请日：2003-04-11

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/28

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，管芯封装包括包括第一表面和第二表面的半导体管芯，以及具有管芯附着区域的引线框架结构以及远离管芯附着区域延伸的多个引线。 管芯附着区域包括一个或多个孔。 成型材料围绕引线框架结构的芯片附接区域和半导体管芯的至少一部分。 成型材料也在一个或多个孔内。

公开(公告)号：US20120181675A1

公开(公告)日：2012-07-19

申请号：US13430347

申请日：2012-03-26

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

IPC: H01L23/495

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US07821124B2

公开(公告)日：2010-10-26

申请号：US11961589

申请日：2007-12-20

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/34 ,  H01L29/76

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: Semiconductor die packages and methods of making them are disclosed. An exemplary package comprises a leadframe having a source lead and a gate lead, and a semiconductor die coupled to the source and gate leads at a first surface of the leadframe. The source lead has a protruding region at a second surface of the leadframe. A molding material is disposed around the semiconductor die, the gate lead, and the source lead such that a surface of the die and a surface of the protruding region are left exposed by the molding material. An exemplary method comprises obtaining the semiconductor die and leadframe, and forming a molding material around at least a portion of the leadframe and die such that a surface of the protruding region is exposed through the molding material.

Abstract translation: 公开了半导体管芯封装及其制造方法。 示例性封装包括具有源极引线和栅极引线的引线框架，以及在引线框架的第一表面处耦合到源极和栅极引线的半导体管芯。 源极引线在引线框架的第二表面具有突出区域。 模塑材料设置在半导体管芯，栅极引线和源极引线周围，使得模具的表面和突出区域的表面被模制材料暴露。 一种示例性方法包括获得半导体管芯和引线框架，以及在引线框架和管芯的至少一部分周围形成模制材料，使得突出区域的表面通过模制材料露出。