公开(公告)号：US07525179B2

公开(公告)日：2009-04-28

申请号：US11448962

申请日：2006-06-06

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/495 ,  H01L23/28

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.

Abstract translation: 公开了一种半导体管芯封装。 在一个实施例中，管芯封装包括包括第一表面和第二表面的半导体管芯，以及具有管芯附着区域的引线框架结构以及远离管芯附着区域延伸的多个引线。 管芯附着区域包括一个或多个孔。 成型材料围绕引线框架结构的芯片附接区域和半导体管芯的至少一部分。 成型材料也在一个或多个孔内。

公开(公告)号：US20070132091A1

公开(公告)日：2007-06-14

申请号：US11299270

申请日：2005-12-09

Applicant: Chung-Lin Wu ,  Rajeev Joshi

Inventor： Chung-Lin Wu ,  Rajeev Joshi

IPC: H01L23/34

CPC classification number: H01L21/561 ,  H01L21/4828 ,  H01L23/4334 ,  H01L23/49548 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2221/68377 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a semiconductor device 30 and a molded upper heat sink 10. The heat sink has an interior surface 16 that faces the semiconductor device and an exterior surface 15 that is at least partially exposed to the ambient environment of the packaged device. An annular planar base 11 surrounds a raised or protruding central region 12. That region is supported above the plane of the base 11 by four sloped walls 13.1-13.4. The walls slope at an acute angle with respect to the planar annular base and incline toward the center of the upper heat sink 10. Around the outer perimeter of the annular base 11 are four support arms 18.1-18.4. The support arms are disposed at an obtuse angle with respect to the interior surface 16 of the planar annular base 11.

Abstract translation: 半导体封装包括半导体器件30和模制的上部散热片10。 散热器具有面向半导体器件的内表面16和至少部分地暴露于封装器件周围环境的外表面15。 环形平面基座11围绕升高或突出的中心区域12。 该区域由基座11的平面支撑在四个倾斜壁13.1-13.4之上。 壁相对于平面环形基座呈锐角倾斜，并朝向上散热片10的中心倾斜。 围绕环形基座11的外周围是四个支撑臂18.1-18.4。 支撑臂相对于平面环形基座11的内表面16以钝角设置。

公开(公告)号：US06836023B2

公开(公告)日：2004-12-28

申请号：US10413796

申请日：2003-04-14

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L2348

CPC classification number: H01L24/10 ,  H01L23/492 ,  H01L24/13 ,  H01L24/37 ,  H01L24/40 ,  H01L2224/05124 ,  H01L2224/05569 ,  H01L2224/05573 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/37147 ,  H01L2224/40225 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A semiconductor die package is disclosed. The die package includes a semiconductor die having a first side and a second side, a vertical transistor, and a bond pad at the first side. A passivation layer having a first aperture is on the first side, and the bond pad is exposed through the first aperture. An underbump metallurgy layer is on and in direct contact with the passivation layer. The underbump metallurgy layer is within the first aperture and contacts the bond pad. A dielectric layer comprising a second aperture is on and in direct contact with the underbump metallurgy layer. A solder structure is on the underbump metallurgy layer and is within the second aperture of the dielectric layer.

Abstract translation: 公开了一种半导体管芯封装。 管芯封装包括具有第一侧和第二侧的半导体管芯，垂直晶体管和第一侧的接合焊盘。 具有第一孔的钝化层位于第一侧上，并且接合焊盘通过第一孔露出。 底涂层冶金层与钝化层直接接触。 底部基底冶金层位于第一孔内并与接合垫接触。 包含第二孔的电介质层处于与底涂层冶金层直接接触的位置。 焊料结构位于底涂层冶金层上，并且位于介电层的第二孔内。

公开(公告)号：US08183088B2

公开(公告)日：2012-05-22

申请号：US12823411

申请日：2010-06-25

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Byoung-Ok Lee

IPC: H01L21/00

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US07772681B2

公开(公告)日：2010-08-10

申请号：US11471291

申请日：2006-06-19

Applicant: Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer

Inventor： Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer

IPC: H01L21/495

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US07332806B2

公开(公告)日：2008-02-19

申请号：US11048314

申请日：2005-01-31

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/34 ,  H01L29/76

CPC classification number: H01L23/495 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/34 ,  H01L24/37 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37599 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/37099

Abstract: A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die. The molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract translation: 半导体管芯封装。 其包括：（a）包括第一表面和第二表面的半导体管芯，（b）源极引线结构，其包括具有主表面的突出区域，所述源极引线结构耦合到所述第一表面，（c）栅极引线结构 耦合到所述第一表面，以及（d）围绕所述源极引线结构和所述半导体管芯的模制材料。 模制材料暴露半导体管芯的第二表面和源极引线结构的主表面。

公开(公告)号：US20100258925A1

公开(公告)日：2010-10-14

申请号：US12823411

申请日：2010-06-25

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Huan Gooi ,  Maria Cristina B. Estacio ,  David Chong ,  Tan Teik Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Yeap Lim ,  Byoung-Ok Lee

IPC: H01L23/28 ,  H01L21/56

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US20070001278A1

公开(公告)日：2007-01-04

申请号：US11471291

申请日：2006-06-19

Applicant: Oseob Jeon ,  Yoonhwa Choi ,  Boon Gooi ,  Maria Cristina Estacio ,  David Chong ,  Tan Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Lim ,  Byoung-Ok Lee

Inventor： Oseob Jeon ,  Yoonhwa Choi ,  Boon Gooi ,  Maria Cristina Estacio ,  David Chong ,  Tan Keng ,  Shibaek Nam ,  Rajeev Joshi ,  Chung-Lin Wu ,  Venkat Iyer ,  Lay Lim ,  Byoung-Ok Lee

IPC: H01L21/00

CPC classification number: H01L24/29 ,  H01L21/561 ,  H01L23/3121 ,  H01L23/4951 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49861 ,  H01L24/32 ,  H01L24/36 ,  H01L24/40 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/97 ,  H01L25/0655 ,  H01L2223/54406 ,  H01L2223/54486 ,  H01L2224/16 ,  H01L2224/291 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/293 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/40245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45169 ,  H01L2224/45565 ,  H01L2224/456 ,  H01L2224/45644 ,  H01L2224/45669 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49113 ,  H01L2224/4943 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85013 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19043 ,  H01L2924/30107 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/37099

Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract translation: 公开了半导体管芯封装。 示例性半导体管芯封装包括预成型衬底。 预成型基板可以具有附接到其上的半导体管芯，并且封装材料可以设置在半导体管芯上方。

公开(公告)号：US07154186B2

公开(公告)日：2006-12-26

申请号：US10803464

申请日：2004-03-18

Applicant: Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

Inventor： Jonathan A. Noquil ,  Seung Yong Choi ,  Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/48

CPC classification number: H01L25/16 ,  H01L23/3128 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A multichip module package uses bond wire with plastic resin on one side of a lead frame to package an integrated circuit and flip chip techniques to attach one or more mosfets to the other side of the lead frame. The assembled multichip module 30 has an integrated circuit controller 14 on a central die pad. Wire bonds 16 extend from contact areas on the integrated circuit to outer leads 2.6 of the lead frame 10. On the opposite, lower side of the central die pad, the sources and gates of the mosfets 24, 26 are bump or stud attached to the half etched regions of the lead frame. The drains 36 of the mosfets and the ball contacts 22.1 on the outer leads are soldered to a printed circuit board.

Abstract translation: 多芯片模块封装在引线框架的一侧使用与塑料树脂的接合线来封装集成电路和倒装芯片技术，以将一个或多个mosfet连接到引线框架的另一侧。 组装的多芯片模块30在中央芯片焊盘上具有集成电路控制器14。 线接合16从集成电路的接触区域延伸到引线框架10的外引线2.6。 在相对的中央管芯焊盘的下侧，MOSFET45,26的源极和栅极是连接到引线框架的半蚀刻区域的凸起或螺柱。 mosfets的漏极36和外引线上的球接触件22.1被焊接到印刷电路板。

公开(公告)号：US07081666B2

公开(公告)日：2006-07-25

申请号：US11051061

申请日：2005-02-04

Applicant: Rajeev Joshi ,  Chung-Lin Wu

Inventor： Rajeev Joshi ,  Chung-Lin Wu

IPC: H01L23/495 ,  H01L23/28

CPC classification number: H01L24/40 ,  H01L21/565 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/37011 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/81801 ,  H01L2224/83801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/13091 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/37099

Abstract: A semiconductor die package is disclosed. In one embodiment, the die package includes a semiconductor die including a first surface and a second surface, and a leadframe structure having a die attach region and a plurality of leads extending away from the die attach region. The die attach region includes one or more apertures. A molding material is around at least portions of the die attach region of the leadframe structure and the semiconductor die. The molding material is also within the one or more apertures.