Secured communication protocol layer for authenticated hardware data access

    公开(公告)号:US12045326B2

    公开(公告)日:2024-07-23

    申请号:US17864724

    申请日:2022-07-14

    CPC classification number: G06F21/31 G06F21/54 G06F21/572

    Abstract: A disclosed method installs an I/O trap protocol to provide an authentication callback function for handling I/O trap events. I/O trap events may include write operations accessing any of one or more identified I/O addresses. An I/O trap event may be registered with the authentication callback function for each of one or more identified I/O addresses. Original values of data may be stored in a memory resource. Any occurrences of an I/O trap event triggers the authentication callback function to perform I/O trap operations. The I/O trap operations may include determining whether the I/O trap event is associated with an approved driver and, if not, restoring data stored at the identified I/O address to an original value. Installing the I/O trap protocol may include installing the I/O trap protocol during a system management mode (SMM) phase of a UEFI boot sequence.

    Storage failover protocol for secure and seamless extended firmware load

    公开(公告)号:US11907071B2

    公开(公告)日:2024-02-20

    申请号:US17739687

    申请日:2022-05-09

    Abstract: An information handling system may include a processor and first non-transitory computer-readable media communicatively coupled to the processor and having stored thereon a basic input/output system (BIOS) core comprising BIOS core firmware sufficient to execute features of a BIOS of the information handling system to a particular portion of BIOS execution and an extension agent. The extension agent may be configured to identify and enumerate a firmware volume of a second non-transitory computer-readable media communicatively coupled to the processor and having stored thereon a BIOS extension comprising BIOS extension firmware for executing completion of BIOS execution from the particular portion of BIOS execution and in response to unavailability of the firmware volume of the second non-transitory computer-readable media, failover to and recover the BIOS extension from extended firmware information stored on a networked storage resource communicatively coupled to the information handling system.

    BIOS NVRAM STORAGE EXTENSION SYSTEM AND METHOD FOR SECURE AND SEAMLESS ACCESS FOR VARIOUS BOOT ARCHITECTURES

    公开(公告)号:US20230333755A1

    公开(公告)日:2023-10-19

    申请号:US17659034

    申请日:2022-04-13

    CPC classification number: G06F3/0631 G06F9/4401 G06F3/0604 G06F3/0679

    Abstract: Systems and methods for providing a storage extension system and method for secure and seamless access by various boot architectures are described. In some embodiments, an Information Handling System (IHS) may include a processor and a BIOS coupled to the processor, the BIOS having program instructions that, upon execution, cause the IHS to receive a request to access a bios storage region of the IHS from a driver, determine whether the device associated with the driver is a platform boot device such that when the boot device is a platform boot device, facilitate access to a native bios storage region of the bios storage region by the driver, and when the boot device is not a platform boot device, facilitate access to an extended bios storage region of the bios storage region by the driver.

    Fault tolerance and debug analysis during a boot process

    公开(公告)号:US11726880B1

    公开(公告)日:2023-08-15

    申请号:US17675215

    申请日:2022-02-18

    CPC classification number: G06F11/1417 G06F9/4403 G06F2201/805

    Abstract: An information handling system may detect an exception, create a hand-off block in an NVMe boot partition in an NVMe device during a pre-extensible firmware interface phase of a boot process, and update the hand-off block with information associated with the exception. The system may also load an exception table to the NVMe boot partition, wherein the exception table includes an index associated with the exception that is mapped to a vector associated with an exception handler, and load the exception handler to the NVMe boot partition, wherein the exception handler resolves the exception.

    Virtual pseudo PCIe (VVP) device nodes for fast reliable OS and virtual memory (VM) boot

    公开(公告)号:US12254322B2

    公开(公告)日:2025-03-18

    申请号:US18364492

    申请日:2023-08-03

    Abstract: In an information handling system that includes one or more PCIe devices, responsive to enumerating a PCIe device and adding the PCIe device to a configuration space of the platform, a mapping entry is added to a device handler mapping table to associate a device handler for the PCIe device with information for accessing the PCIe device. If the PCIe device fails to enumerate in a boot path, a virtual pseudo PCIe (VPP) node corresponding to the PCIe device may be created and enumerated to enable the boot to complete. Upon subsequently detecting and enumerating the actual, physical PCIe device, the VPP node and the PCIe device may be connected to enable the full functionality of the PCIe device without re-booting the platform.

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