Full-chip extraction of interconnect parasitic data
    13.
    发明授权
    Full-chip extraction of interconnect parasitic data 有权
    全芯片提取互连寄生数据

    公开(公告)号:US06463571B1

    公开(公告)日:2002-10-08

    申请号:US09808549

    申请日:2001-03-14

    Inventor: David A. Morgan

    CPC classification number: G06F17/5036

    Abstract: In this method for hierarchical extraction of interconnect parasitic data for integrated circuits, a representation of coupled interconnects and polygon data copied from an upper level to a lower level is simplified so that the coupled interconnects and the polygon data are considered to be ground wires. This method also features instance-specific management of hardmac data from copied hardmac views to create SPEF files using both chip level and macro level back-annotation in a hierarchical representation.

    Abstract translation: 在用于集成电路的互连寄生数据的层次提取的方法中,简化了从上层复制到较低层的耦合互连和多边形数据的表示,使得耦合互连和多边形数据被认为是接地线。 该方法还具有针对复制硬件视图的硬件数据实例特定管理,以在层次表示中使用芯片级和宏级反向注释来创建SPEF文件。

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