公开(公告)号：US20160293568A1

公开(公告)日：2016-10-06

申请号：US15070303

申请日：2016-03-15

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan

IPC: H01L23/00 ,  H01L23/367 ,  H01L25/065 ,  H01L21/48 ,  H01L21/288

CPC classification number: H01L23/047 ,  H01L21/288 ,  H01L21/486 ,  H01L21/4867 ,  H01L21/50 ,  H01L23/057 ,  H01L23/142 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/4924 ,  H01L23/49861 ,  H01L23/49866 ,  H01L24/13 ,  H01L24/27 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/80 ,  H01L24/83 ,  H01L25/0655 ,  H01L2224/2731 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83447 ,  H01L2224/8384 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/0461 ,  H01L2924/0469 ,  H01L2924/1421 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/15763 ,  H01L2924/16152 ,  H01L2924/16598 ,  H01L2924/171 ,  H01L2924/181 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20108 ,  H01L2924/3025 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device package that incorporates a combination of ceramic, organic, and metallic materials that are coupled using silver is provided. The silver is applied in the form of fine particles under pressure and a low temperature. After application, the silver forms a solid that has a typical melting point of silver, and therefore the finished package can withstand temperatures significantly higher than the manufacturing temperature. Further, since the silver is an interfacial material between the various combined materials, the effect of differing material properties between ceramic, organic, and metallic components, such as coefficient of thermal expansion, is reduced due to low temperature of bonding and the ductility of the silver.

Abstract translation: 提供了结合使用银耦合的陶瓷，有机和金属材料的组合的半导体器件封装。 银在加压和低温下以微粒的形式施加。 应用后，银形成具有典型的银熔点的固体，因此成品封装可承受明显高于制造温度的温度。 此外，由于银是各种组合材料之间的界面材料，所以陶瓷，有机和金属组分之间的不同材料性质（如热膨胀系数）的影响由于低粘结温度和 银。

公开(公告)号：US09300254B2

公开(公告)日：2016-03-29

申请号：US14316484

申请日：2014-06-26

Applicant: Freescale Semiconductor, Inc.

Inventor： Mahesh K. Shah ,  Jerry L. White ,  Li Li ,  Hussain H. Ladhani ,  Audel A. Sanchez ,  Lakshminarayan Viswanathan ,  Fernando A. Santos

IPC: H03F3/213 ,  H03F1/30 ,  H03H1/00 ,  H03F3/195

CPC classification number: H03F1/0288 ,  H01L23/3107 ,  H01L23/49562 ,  H01L23/642 ,  H01L23/66 ,  H01L2223/665 ,  H01L2223/6655 ,  H01L2223/6666 ,  H01L2224/49175 ,  H01L2924/0002 ,  H03F1/0283 ,  H03F1/30 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F3/213 ,  H03F2200/267 ,  H03F2200/451 ,  H03F2200/555 ,  H03F2203/21103 ,  H03F2203/21106 ,  H03F2203/21139 ,  H03H1/00 ,  H03H7/38 ,  H03H2001/0021 ,  H05K7/005 ,  H01L2924/00

Abstract: An embodiment of a radio-frequency (RF) device includes at least one transistor, a package, and a surface-mountable capacitor. The package contains the at least one transistor and includes at least one termination. The surface-mountable capacitor is coupled in a shunt configuration between the at least one transistor and a power supply terminal of the device to decouple the at least one transistor from a power supply.

Abstract translation: 射频（RF）器件的一个实施例包括至少一个晶体管，封装和表面贴装电容器。 该封装包含至少一个晶体管，并且包括至少一个端接。 表面安装电容器以至少一个晶体管和该器件的电源端之间的分流配置耦合，以将至少一个晶体管与电源分离。

公开(公告)号：US10573594B2

公开(公告)日：2020-02-25

申请号：US15097014

申请日：2016-04-12

Applicant: Freescale Semiconductor, Inc.

Inventor： Peter H. Aaen ,  David J. Dougherty ,  Manuel F. Romero ,  Lakshminarayan Viswanathan

IPC: H01L23/522 ,  H03F3/21 ,  H01L23/495 ,  H03F3/195 ,  H03F3/24 ,  H01L23/552 ,  H01L23/66 ,  H01L23/64 ,  H03F1/02 ,  H01L23/29 ,  H03F3/213

Abstract: A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a Doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. The isolation feature can take the form of a structure that is constructed of a conductive material coupled to ground and which separates the elements of the amplifier. The isolation feature can be included in a variety of semiconductor packages, including air cavity packages and overmolded packages. Through the use of the isolation feature provided by embodiments of the present invention a significant improvement in signal isolation between amplifier elements is realized, thereby improving performance of the dual-path amplifier.

公开(公告)号：US10109594B2

公开(公告)日：2018-10-23

申请号：US15136326

申请日：2016-04-22

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Michael E. Watts ,  David F. Abdo

IPC: H01L23/552 ,  H01L23/057 ,  H01L23/66 ,  H01L21/52 ,  H01L23/053 ,  H01L23/538 ,  H01L23/58 ,  H01L25/065 ,  H01L25/00 ,  H03F1/02 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H01L23/00

Abstract: A system and method for packaging a semiconductor device that includes a structure to reduce electromagnetic coupling are presented. The semiconductor device is formed on a substrate. A cover is affixed to the substrate so as to extend over the semiconductor device. An isolation structure of electrically conductive material is coupled to the cover in between components of the semiconductor device, with the isolation structure being configured to reduce inductive coupling between those components during an operation of the semiconductor device. In one version, the isolation structure includes a first leg extending from a ground connection along a side wall of the cover to a cross member contiguous with a primary cover wall that extends over the semiconductor device between the components to be isolated electromagnetically.

公开(公告)号：US09875987B2

公开(公告)日：2018-01-23

申请号：US15247393

申请日：2016-08-25

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Jaynal A. Molla

IPC: H01L23/00 ,  H01L29/16 ,  H01L21/48 ,  H01L29/20 ,  H01L23/66 ,  H01L23/48 ,  H01L21/78 ,  H01L23/31 ,  H01L23/36 ,  H01L23/367 ,  H01L23/482 ,  H01L21/683 ,  H01L23/495 ,  H01L21/56

CPC classification number: H01L24/83 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/4827 ,  H01L23/49513 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/741 ,  H01L24/743 ,  H01L24/92 ,  H01L24/94 ,  H01L29/16 ,  H01L29/2003 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/03312 ,  H01L2224/0332 ,  H01L2224/03436 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03505 ,  H01L2224/04026 ,  H01L2224/05009 ,  H01L2224/05018 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05551 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05794 ,  H01L2224/05839 ,  H01L2224/05844 ,  H01L2224/05847 ,  H01L2224/05855 ,  H01L2224/05864 ,  H01L2224/05887 ,  H01L2224/0589 ,  H01L2224/05893 ,  H01L2224/27002 ,  H01L2224/2731 ,  H01L2224/27312 ,  H01L2224/2732 ,  H01L2224/27436 ,  H01L2224/27438 ,  H01L2224/27505 ,  H01L2224/29006 ,  H01L2224/29011 ,  H01L2224/29012 ,  H01L2224/29015 ,  H01L2224/29017 ,  H01L2224/2908 ,  H01L2224/29082 ,  H01L2224/29083 ,  H01L2224/29084 ,  H01L2224/291 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29113 ,  H01L2224/29116 ,  H01L2224/29117 ,  H01L2224/29118 ,  H01L2224/2912 ,  H01L2224/29124 ,  H01L2224/29138 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/2918 ,  H01L2224/29184 ,  H01L2224/2919 ,  H01L2224/29193 ,  H01L2224/2929 ,  H01L2224/29294 ,  H01L2224/293 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29387 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/29499 ,  H01L2224/296 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/741 ,  H01L2224/83191 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8346 ,  H01L2224/83815 ,  H01L2224/8384 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/1016 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1421 ,  H01L2924/15738 ,  H01L2924/15747 ,  H01L2924/1576 ,  H01L2924/3512 ,  H01L2224/27 ,  H01L2224/11 ,  H01L2924/0665 ,  H01L2924/014 ,  H01L2924/01015 ,  H01L2924/01048 ,  H01L2924/01014 ,  H01L2924/01032 ,  H01L2924/0105 ,  H01L2924/01047 ,  H01L2924/01028 ,  H01L2924/01027 ,  H01L2924/01026 ,  H01L2224/03 ,  H01L2224/05099 ,  H01L2924/01006 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/01005 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2221/68304 ,  H01L21/304 ,  H01L2224/83 ,  H01L2924/0781 ,  H01L2924/00 ,  H01L2224/034 ,  H01L2221/68368 ,  H01L2224/274

Abstract: An electronic device includes a semiconductor die having a lower surface, a sintered metallic layer underlying the lower surface of the semiconductor die, a conductive layer underlying the sintered metallic layer, and a conductive substrate underlying the conductive layer.

公开(公告)号：US09824995B2

公开(公告)日：2017-11-21

申请号：US14500319

申请日：2014-09-29

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Michael E. Watts

IPC: H05K7/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/66 ,  H01L23/057

CPC classification number: H01L24/49 ,  H01L23/057 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/37 ,  H01L24/40 ,  H01L24/48 ,  H01L24/50 ,  H01L24/73 ,  H01L2224/131 ,  H01L2224/16245 ,  H01L2224/2919 ,  H01L2224/32245 ,  H01L2224/37599 ,  H01L2224/40157 ,  H01L2224/45099 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2224/49109 ,  H01L2224/49176 ,  H01L2224/50 ,  H01L2224/73229 ,  H01L2224/83101 ,  H01L2224/8384 ,  H01L2224/84801 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/161 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/30111 ,  H01L2924/014 ,  H01L2224/37099

Abstract: A packaged RF device is provided that utilizes flexible circuit leads. The RF device includes at least one integrated circuit (IC) die configured to implement the RF device. The IC die is contained inside a package. In accordance with the embodiments described herein, a flexible circuit is implemented as a lead. Specifically, the flexible circuit lead is coupled to the at least one IC die inside the package and extends to outside the package, the flexible circuit lead thus providing an electrical connection to the at least one IC die inside the package.

公开(公告)号：US20160308010A1

公开(公告)日：2016-10-20

申请号：US15173487

申请日：2016-06-03

Applicant: Freescale Semiconductor, Inc.

Inventor： Lakshminarayan Viswanathan ,  Bruce M. Green ,  Darrell G. Hill ,  L. M. Mahalingam

IPC: H01L29/417 ,  H01L23/373 ,  H01L23/48 ,  H01L29/778 ,  H01L29/20

CPC classification number: H01L23/373 ,  H01L21/042 ,  H01L21/0475 ,  H01L21/28 ,  H01L21/32051 ,  H01L21/762 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/05 ,  H01L24/29 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H01L2224/04026 ,  H01L2224/29026 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.

Abstract translation: 半导体器件的实施例包括半导体衬底，其包括主体衬底和上表面，有源区域，半导体衬底中的由凹陷表面局部限定的衬底开口，以及设置在半导体衬底上的导热层 其在有源区域内在凹入表面和半导体衬底的一部分之间延伸。 制造半导体器件的方法包括限定有源区域，在有源区域中的沟道上形成栅电极，在栅电极的相对侧上的有源区域中形成源电极和漏电极，蚀刻栅电极的衬底开口 所述半导体衬底由所述凹陷表面部分地限定，并且在所述半导体衬底上沉积导热层，所述导热层在所述沟道上在所述凹陷表面和所述半导体衬底的一部分之间延伸。

公开(公告)号：US09425161B2

公开(公告)日：2016-08-23

申请号：US14808779

申请日：2015-07-24

Applicant: FREESCALE SEMICONDUCTOR, INC.

Inventor： Lakshminarayan Viswanathan ,  L. M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC: H01L23/52 ,  H01L23/00 ,  B23K20/02 ,  B23K35/02 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  B23K20/00 ,  H01L23/31 ,  H05K3/28

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US20160225713A1

公开(公告)日：2016-08-04

申请号：US15097014

申请日：2016-04-12

Applicant: Freescale Semiconductor, Inc.

Inventor： Peter H. Aaen ,  David J. Dougherty ,  Manuel F. Romero ,  Lakshminarayan Viswanathan

IPC: H01L23/522 ,  H03F3/213 ,  H03F1/02 ,  H03F3/21 ,  H01L23/495 ,  H01L23/29

Abstract: A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a Doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. The isolation feature can take the form of a structure that is constructed of a conductive material coupled to ground and which separates the elements of the amplifier. The isolation feature can be included in a variety of semiconductor packages, including air cavity packages and overmolded packages. Through the use of the isolation feature provided by embodiments of the present invention a significant improvement in signal isolation between amplifier elements is realized, thereby improving performance of the dual-path amplifier.

Abstract translation: 提供了减少在封装内体现的半导体器件的元件之间的电磁耦合的单个半导体器件封装。 对于诸如Doherty功率放大器的双通道放大器，将载波放大器元件与峰值放大器元件分离的隔离特征包括在半导体器件封装内。 隔离特征可以采取由耦合到地并且分离放大器的元件的导电材料构成的结构的形式。 隔离特征可以包括在各种半导体封装中，包括气腔封装和包覆成型的封装。 通过使用由本发明的实施例提供的隔离特征，实现放大器元件之间的信号隔离的显着改进，从而提高双路放大器的性能。

公开(公告)号：US20150235933A1

公开(公告)日：2015-08-20

申请号：US14184266

申请日：2014-02-19

Applicant: Freescale Semiconductor, Inc.

Inventor： Hussain H. Ladhani ,  Lu Li ,  Mahesh K. Shah ,  Lakshminarayan Viswanathan ,  Michael E. Watts

IPC: H01L23/498 ,  H01L21/48 ,  H01L25/00 ,  H03F3/193 ,  H03F3/21

CPC classification number: H01L21/4853 ,  H01L23/66 ,  H01L25/50 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H03F1/565 ,  H03F3/193 ,  H03F3/195 ,  H03F3/21 ,  H03F2200/423 ,  H03F2200/451 ,  H01L2924/00014

Abstract: A semiconductor device, related package, and method of manufacturing same are disclosed. In at least one embodiment, the semiconductor device includes a radio frequency (RF) power amplifier transistor having a first port, a second port, and a third port. The semiconductor device also includes an output lead, a first output impedance matching circuit between the second port and the output lead, and a first additional circuit coupled between the output lead and a ground terminal. At least one component of the first additional circuit is formed at least in part by way of one or more of a plurality of castellations and a plurality of vias.

Abstract translation: 公开了一种半导体器件，相关封装及其制造方法。 在至少一个实施例中，半导体器件包括具有第一端口，第二端口和第三端口的射频（RF）功率放大器晶体管。 半导体器件还包括输出引线，第二端口和输出引线之间的第一输出阻抗匹配电路，以及耦合在输出引线和接地端子之间的第一附加电路。 第一附加电路的至少一个部件至少部分地通过多个城堡和多个通孔中的一个或多个形成。