公开(公告)号：US20190214308A1

公开(公告)日：2019-07-11

申请号：US15868229

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Qun Gao ,  Scott Beasor ,  Kyung Bum Koo ,  Ankur Arya

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.

公开(公告)号：US10886178B2

公开(公告)日：2021-01-05

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Annie Levesque ,  Qun Gao ,  Hui Zang ,  Rishikesh Krishnan ,  Bharat Krishnan ,  Curtis Durfee

IPC: H01L29/167 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L21/02 ,  H01L29/40 ,  H01L23/535

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US10014364B1

公开(公告)日：2018-07-03

申请号：US15460914

申请日：2017-03-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qun Gao ,  Anthony Chou ,  Stephen Furkay ,  Naved Siddiqui

IPC: H01L49/02 ,  H01L21/3213 ,  H01L27/06 ,  H01L35/14 ,  H01L35/32

CPC classification number: H01L28/24 ,  H01L35/14 ,  H01L35/32

Abstract: Device structures and fabrication methods for an on-chip resistor. A first Seebeck terminal is arranged to overlap with first and second resistor bodies of the on-chip resistor. A second Seebeck terminal is also arranged to overlap with the first and second resistor bodies. The second Seebeck terminal has a spaced relationship with the first Seebeck terminal along a length of the first and second resistor bodies. The temperature coefficient of resistance of the on-chip resistor is based at least in part on a Seebeck coefficient of first and second Seebeck terminals.