公开(公告)号：US20140183720A1

公开(公告)日：2014-07-03

申请号：US13731305

申请日：2012-12-31

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Scott Beasor ,  Jay Strane ,  Man Fai Ng ,  Brett H. Engel ,  Chang Yong Xiao ,  Michael P. Belyansky ,  Tsung-Liang Chen ,  Kyung Bum Koo

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/48 ,  H01L21/76832 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Methods of manufacturing semiconductor integrated circuits having a compressive nitride layer are disclosed. In one example, a method of fabricating an integrated circuit includes depositing an aluminum layer over a semiconductor substrate, depositing a tensile silicon nitride layer or a neutral silicon nitride layer over the aluminum layer, and depositing a compressive silicon nitride layer over the tensile silicon nitride layer or the neutral silicon nitride layer. The compressive silicon nitride layer is deposited at a thickness that is at least about twice a thickness of the tensile silicon nitride layer or the neutral silicon nitride layer. Further, there is no delamination present at an interface between the aluminum layer and the tensile silicon nitride layer or the neutral silicon nitride layer, or at an interface between tensile silicon nitride layer or the neutral silicon nitride layer and the compressive nitride layer.

Abstract translation: 公开了具有压缩氮化物层的半导体集成电路的制造方法。 在一个示例中，制造集成电路的方法包括在半导体衬底上沉积铝层，在铝层上沉积拉伸氮化硅层或中性氮化硅层，以及在抗拉氮化硅上沉积压缩氮化硅层 层或中性氮化硅层。 压缩氮化硅层以至少约为拉伸氮化硅层或中性氮化硅层厚度的约两倍的厚度沉积。 此外，在铝层和拉伸氮化硅层或中性氮化硅层之间的界面处，或者在拉伸氮化硅层或中性氮化硅层与压缩氮化物层之间的界面处没有分层存在。

公开(公告)号：US10832965B2

公开(公告)日：2020-11-10

申请号：US15868229

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Qun Gao ,  Scott Beasor ,  Kyung Bum Koo ,  Ankur Arya

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.

公开(公告)号：US20190214308A1

公开(公告)日：2019-07-11

申请号：US15868229

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Qun Gao ,  Scott Beasor ,  Kyung Bum Koo ,  Ankur Arya

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/161 ,  H01L21/762 ,  H01L21/311 ,  H01L21/3105

Abstract: Integrated circuit devices include trenches in a material layer that divide the material layer into fins. With such devices, an insulator partially fills the trenches and contacts the material layer. The top surface of the insulator (e.g., the surface opposite where the insulator contacts the material layer) has a convex dome shape between at least two of the fins. The dome shape has a first thickness from (from the bottom of the trench) where the insulator contacts the fins, and a second thickness that is greater than the first thickness where the insulator is between the fins. Further, there is a maximum thickness difference between the first and second thicknesses at the midpoint between the fins (e.g., the highest point of the dome shape is at the midpoint between the fins). Also, the top surface of the first insulator has concave divots where the first insulator contacts the fins.