公开(公告)号：US10818792B2

公开(公告)日：2020-10-27

申请号：US16106291

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Daniel Chanemougame

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/768 ,  H01L21/8234

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A layer stack includes nanosheet channel layers arranged to alternate with sacrificial layers. First and second gate structures are formed that extend across the layer stack and that are separated by a first gap. First and second sidewall spacers are formed over the layer stack and within the first gap respectively adjacent to the first and second gate structures, and the layer stack is subsequently etched to form first and second body features that are separated by a second gap. The sacrificial layers are recessed relative to the nanosheet channel layers to define indents in the first and second body features, and the first and second sidewall spacers are subsequently removed. After removing the first and second sidewall spacers, a conformal layer is deposited in the second gap that fills the indents to define inner spacers.

公开(公告)号：US10770585B2

公开(公告)日：2020-09-08

申请号：US16139917

申请日：2018-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Andre Labonte ,  Daniel Chanemougame

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/768 ,  H01L21/28 ,  H01L29/08 ,  H01L29/49 ,  H01L23/532

Abstract: A device including a self-aligned buried contact between spacer liners and isolated from a pull down (PD)/pull-up (PU) shared gate and an n-channel field-effect transistor (NFET) pass gate (PG) gate and method of production thereof. Embodiments include first and second high-k/metal gate (HKMG) structures over a first portion of a substrate, and a third HKMG structure over a second portion of the substrate; an inter-layer dielectric (ILD) over a portion of the substrate and on sidewalls of the first, second and third HKMG structures; a spacer liner on sidewalls of the ILD between the second and third HKMG structures; and a buried contact layer between the spacer liner and in a portion of the substrate.

公开(公告)号：US10685874B1

公开(公告)日：2020-06-16

申请号：US16220565

申请日：2018-12-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Lei Sun ,  Lars Liebmann ,  Daniel Chanemougame ,  Guillaume Bouche

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.

公开(公告)号：US20200035567A1

公开(公告)日：2020-01-30

申请号：US16047044

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Ruilong Xie ,  Chanro Park ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L27/092

Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. When a first WFM surrounding the second active nanostructure is removed as part of a WFM patterning process, creating a discontinuity in the first metal. The pillar or the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. The isolation pillar creates a gate cut isolation in a selected gate region, and can be shortened in another gate region to allow for gate sharing between adjacent FETs.

公开(公告)号：US10522403B2

公开(公告)日：2019-12-31

申请号：US15868479

申请日：2018-01-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jason E. Stephens ,  Daniel Chanemougame ,  Ruilong Xie ,  Lars W. Liebmann ,  Gregory A. Northrop

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to middle of the line self-aligned direct pattern contacts and methods of manufacture. The structures described herein include: at least one gate structure with a metallization and source/drain regions; a source/drain contact in electrical connection with the source/drain regions, respectively; and a contact structure with a re-entrant profile in electrical connection with the source/drain contact and the metallization of the at least one gate structure, respectively.

公开(公告)号：US10510620B1

公开(公告)日：2019-12-17

申请号：US16047043

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Steven R. Soss ,  Steven J. Bentley ,  Julien Frougier ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/092 ,  H01L27/11

Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. A first WFM for one FET is deposited over the first active nanostructure, the pillar and the second active nanostructure. The first WFM is removed from a part of the pillar. The removing creates a discontinuity in the first WFM over the first active nano structure from the first WFM over the second active nanostructure but leaves the first WFM on sidewalls of the pillar. When the first WFM surrounding the second active nanostructure is removed, the pillar and the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. Depositing a second WFM surrounding the second active nanostructure and the isolation pillar forms part of the gate for the second FET and couples the FETs together.

公开(公告)号：US20190326165A1

公开(公告)日：2019-10-24

申请号：US15961337

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Daniel Chanemougame ,  Steven Soss ,  Lars Liebmann ,  Hui Zang ,  Shesh Mani Pandey

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/522 ,  H01L23/528

Abstract: Methods and structures that include a vertical-transport field-effect transistor. First and second semiconductor fins are formed that project vertically from a bottom source/drain region. A first gate stack section is arranged to wrap around a portion of the first semiconductor fin, and a second gate stack section is arranged to wrap around a portion of the second semiconductor fin. The first gate stack section is covered with a placeholder structure. After covering the first gate stack section with the placeholder structure, a metal gate capping layer is deposited on the second gate stack section. After depositing the metal gate capping layer on the second gate stack section, the placeholder structure is replaced with a contact that is connected with the first gate stack section.

公开(公告)号：US20190312116A1

公开(公告)日：2019-10-10

申请号：US15947991

申请日：2018-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emilie Bourjot ,  Daniel Chanemougame ,  Steven Bentley

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Methods of forming contacts for vertical-transport field-effect transistors and structures for a vertical-transport field-effect transistor and contact. An interlayer dielectric layer is deposited over a gate stack, and a first opening is formed in the interlayer dielectric layer and penetrates through the gate stack to cut the gate stack into a first section and a second section. A dielectric pillar is formed in the first opening and is arranged between the first section of the gate stack and the second section of the gate stack. Second and third openings are formed in the interlayer dielectric layer that penetrate to the gate stack and that are divided by the dielectric pillar. A first contact in the second opening is coupled with the first section of the gate stack, and a second contact in the third opening is coupled with the second section of the gate stack.

公开(公告)号：US10381354B2

公开(公告)日：2019-08-13

申请号：US15861161

申请日：2018-01-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Chanemougame ,  Emilie Bourjot

IPC: H01L27/11 ,  H01L29/78 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417

Abstract: One illustrative IC product disclosed herein includes a first merged doped source/drain region that includes first and second doped regions and an isolation structure positioned adjacent the first doped region. In this example, the product also includes a contact structure positioned adjacent the isolation structure, wherein the contact structure includes a first portion positioned below an upper surface of the first merged doped source/drain region and a second portion positioned above the upper surface, wherein the first portion physically contacts both the first and second doped regions. The product also includes a layer of insulating material positioned on and in physical contact with a portion of an upper surface of the first portion of the contact structure.

公开(公告)号：US10332803B1

公开(公告)日：2019-06-25

申请号：US15973817

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Edward J. Nowak ,  Bipul C. Paul ,  Steven R. Soss ,  Julien Frougier ,  Daniel Chanemougame ,  Lars W. Liebmann

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092

Abstract: Various embodiments relate to gate-all-around (GAA) transistors and methods of forming such transistors. In some embodiments, a method performed on a precursor structure includes selectively removing a sacrificial nanosheet to open a vertical gap between a pair of semiconductor nanosheets; forming a first work function metal to surround the precursor nanosheet stack and fin, the first work function metal filling the vertical gap between the pair of semiconductor nano sheets; selectively removing first work function metal surrounding the fin while preserving an entirety of first work function metal surrounding the nanosheet stack; and forming a second work function metal: over a remaining portion of the first work function metal on nanosheet stack, and surrounding the fin, where first work function metal includes a different material than second work function metal.