公开(公告)号：US20150108586A1

公开(公告)日：2015-04-23

申请号：US14579122

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jerome Ciavatti ,  Johannes M. van Meer

IPC: H01L29/78 ,  H01L29/36 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/78 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/36 ,  H01L29/66492 ,  H01L29/7833

Abstract: One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

Abstract translation: 本文公开的一个示例性器件包括位于栅极结构的相对侧上的有源区域中的多个源极/漏极区域，每个源极/漏极区域在晶体管的栅极长度方向上具有横向宽度，并且多个卤素 区域，其中每个光晕区域位于多个源极/漏极区域中的一个的横向宽度的一部分但不是全部的下方。 本文公开的方法包括在有源区域中形成多个晕轮注入区域，其中每个晕轮植入区域的外边缘与隔离区域的相邻内边缘横向间隔开。

公开(公告)号：US20150097197A1

公开(公告)日：2015-04-09

申请号：US14045983

申请日：2013-10-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michael Ganz ,  Johannes M. van Meer ,  Bharat V. Krishnan

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66795 ,  H01L29/7848

Abstract: Embodiments of the present invention provide an improved finFET and methods of fabrication. A sigma cavity is used with an n-type finFET to allow multiple epitaxial layers to be disposed adjacent to a finFET gate. In some embodiments, stacking faults may be formed in the epitaxial layers using a stress memorization technique.

Abstract translation: 本发明的实施例提供了改进的finFET和制造方法。 Σ型空腔与n型finFET一起使用，以允许多个外延层邻近finFET栅极设置。 在一些实施例中，可以使用应力记忆技术在外延层中形成堆垛层错。

公开(公告)号：US20150037945A1

公开(公告)日：2015-02-05

申请号：US13956475

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes M. van Meer ,  Michael J. Hargrove ,  Christian Gruensfelder ,  Yanxiang Liu ,  Srikanth B. Samavedam

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/02636 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/1608 ,  H01L29/66795 ,  H01L29/7855

Abstract: Approaches for enabling epitaxial growth of silicon fins in a device (e.g., a fin field effect transistor device (FinFET)) are provided. Specifically, approaches are provided for forming a set of silicon fins for a FinFET device, the FinFET device comprising: a set of gate structures formed over a substrate, each of the set of gate structures including a capping layer and a set of spacers; an oxide fill formed over the set of gate structures; a set of openings formed in the device by removing the capping layer and the set of spacers from one or more of the set of gate structures; a silicon material epitaxially grown within the set of openings in the device and then planarized; and wherein the oxide fill is etched to expose the silicon material and form the set of fins.

公开(公告)号：US20150021702A1

公开(公告)日：2015-01-22

申请号：US13947439

申请日：2013-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang Liu ,  Johannes M. van Meer ,  Xiaodong Yang ,  Manfred J. Eller

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/30625 ,  H01L21/31053 ,  H01L29/0653 ,  H01L29/7846

Abstract: A semiconductor structure with an improved shallow trench isolation (STI) region and method of fabrication is disclosed. The STI region comprises a lower portion filled with oxide and an upper portion comprising a high Young's modulus (HYM) liner disposed on the lower portion and trench sidewalls and filled with oxide. The HYM liner is disposed adjacent to source-drain regions, and serves to reduce stress relaxation within the shallow trench isolation (STI) oxide, which has a relatively low Young's modulus and is soft. Hence, the HYM liner serves to increase the desired stress imparted by the embedded stressor source-drain regions, which enhances carrier mobility, thus increasing semiconductor performance.

Abstract translation: 公开了具有改进的浅沟槽隔离（STI）区域和制造方法的半导体结构。 STI区域包括填充有氧化物的下部分和包括设置在下部分上的高杨氏模量（HYM）衬垫和沟槽侧壁并填充有氧化物的上部部分。 HYM衬垫设置在源 - 漏区附近，用于减少浅沟槽隔离（STI）氧化物中的应力松弛，其具有较低的杨氏模量并且柔软。 因此，HYM衬垫用于增加由嵌入式应力源源极 - 漏极区域施加的所需应力，这增强了载流子迁移率，从而提高了半导体性能。