公开(公告)号：US20200185292A1

公开(公告)日：2020-06-11

申请号：US16358203

申请日：2019-03-19

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Ryohei Urata ,  Teckgyu Kang

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L21/56

Abstract: Integrated circuit substrates having features for containing liquid adhesive, and methods for fabricating such substrates, are provided. A device can include a first substrate layer and a second substrate layer adhered to the first substrate layer such that a portion of the top surface of the first substrate layer is exposed to define a bottom of a cavity, and an edge of the second substrate layer adjacent to the exposed top surface of the first substrate layer defines an edge of the cavity. The device can include an integrated circuit die adhered to the exposed top surface of first substrate layer with a liquid adhesive. The first substrate layer can define a trench in the bottom of the cavity between a region of the integrated circuit die and the edge of the cavity such that the trench can receive bleed-out of the liquid adhesive from between the integrated circuit die and the top surface of the first substrate layer.

公开(公告)号：US20190327859A1

公开(公告)日：2019-10-24

申请号：US15957161

申请日：2018-04-19

Applicant: Google LLC

Inventor： Madhusudan Krishnan Iyengar ,  Christopher Gregory Malone ,  Yuan Li ,  Jorge Padilla ,  Woon Seong Kwon ,  Teckgyu Kang ,  Norman Paul Jouppi

IPC: H05K7/20

Abstract: A server tray package includes a motherboard assembly that includes a plurality of data center electronic devices, the plurality of data center electronic devices including at least one heat generating processor device; and a liquid cold plate assembly. The liquid cold plate assembly includes a base portion mounted to the motherboard assembly, the base portion and motherboard assembly defining a volume that at least partially encloses the plurality of data center electronic devices; and a top portion mounted to the base portion and including a heat transfer member shaped to thermally contact the heat generating processor device, the heat transfer member including an inlet port and an outlet port that are in fluid communication with a cooling liquid flow path defined through the heat transfer member.

公开(公告)号：US20190172767A1

公开(公告)日：2019-06-06

申请号：US16000637

申请日：2018-06-05

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Phillip La ,  Michael Trent Wise

IPC: H01L23/24 ,  H01L21/67 ,  H01L23/00

Abstract: A stiffener apparatus for reducing warpage of an integrated circuit package during heating and cooling are provided. The stiffener apparatus includes an IC substrate configured to receive an IC die on a top side of the IC substrate. The stiffener apparatus includes a primary stiffener ring adhered to the top side of the IC substrate and defining an opening in a region of the IC die such that the primary stiffener ring surrounds the region of the IC die. The primary stiffener ring defines a plurality of grooves. The stiffener apparatus includes a secondary stiffener ring having a plurality of catches configured to engage with the plurality of grooves to removably attach the secondary stiffener ring to the primary stiffener ring on a side of the primary stiffener ring opposite the IC substrate. A method of using a stiffener apparatus during a manufacturing operation is also provided.

公开(公告)号：US20180299628A1

公开(公告)日：2018-10-18

申请号：US15948435

申请日：2018-04-09

Applicant: Google LLC

Inventor： Hong Liu ,  Ryohei Urata ,  Woon Seong Kwon ,  Teckgyu Kang

IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H05K3/34 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15 ,  H05K1/18

Abstract: Signal integrity in high-speed applications is dependent on both the underlying device performance and electronic packaging methods. The maturity of chip-on-board (COB) packaging technology using wire bonding makes it a cost beneficial option for the mass production of high-speed optical transceivers. However, wire bonding introduces parasitic inductance associated with the length of the bond wires that limits the scalability of the system for higher data throughput. A high-speed optical transceiver package according to a first proposed configuration minimizes packaging related parasitic inductance by vertically integrating components using flip-chip bonding. A high-speed optical transceiver package according to a second proposed configuration minimizes packaging related parasitic inductance with horizontal tiling of components using a chip carrier and flip-chip bonding.

公开(公告)号：US20240250082A1

公开(公告)日：2024-07-25

申请号：US18624411

申请日：2024-04-02

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Teckgyu Kang ,  Yujeong Shim

IPC: H01L25/18 ,  H01L23/498 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/0652 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.

公开(公告)号：US20210249384A1

公开(公告)日：2021-08-12

申请号：US16788994

申请日：2020-02-12

Applicant: Google LLC

Inventor： Nam Hoon Kim ,  Woon Seong Kwon ,  Houle Gan ,  Yujeong Shim ,  Mikhail Popovich ,  Teckgyu Kang

IPC: H01L25/065 ,  H01L49/02

Abstract: The technology relates to an integrated circuit (IC) package. The IC package may include a packaging substrate, an IC die, and an integrated voltage regulator die. The IC die may include a metal layer and a silicon layer. The metal layer may be connected to the packaging substrate. The integrated voltage regulator die may be positioned adjacent to the silicon layer and connected to the packaging substrate via one or more through mold vias or through dielectric vias. The IC die may be an application specific integrated circuit (ASIC) die.

公开(公告)号：US10896873B2

公开(公告)日：2021-01-19

申请号：US16358197

申请日：2019-03-19

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L23/522 ,  H01L49/02

Abstract: A processor assembly and a system including a processor assembly are disclosed. The processor assembly includes an interposer disposed on a substrate, an integrated circuit disposed on the interposer, a memory circuit disposed on the interposer and coupled to the integrated circuit, and a capacitor embedded in the interposer. The capacitor includes at least a first non-planar conductor structure and a second non-planar conductor structure separated by a non-planar dielectric structure. The capacitor includes a first capacitor terminal electrically coupling the first non-planar conductor structure to a first voltage terminal in the integrated circuit. The capacitor includes a second capacitor terminal electrically coupling the second non-planar conductor structure to a second voltage terminal in the integrated circuit. The capacitor includes an oxide layer electrically isolating the capacitor from the interposer.

公开(公告)号：US20190312002A1

公开(公告)日：2019-10-10

申请号：US15948456

申请日：2018-04-09

Applicant: Google LLC

Inventor： Woon Seong Kwon ,  Nam Hoon Kim ,  Teckgyu Kang

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

Abstract: Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections.