公开(公告)号：US11461175B1

公开(公告)日：2022-10-04

申请号：US17447954

申请日：2021-09-17

Applicant: Graphcore Limited

Inventor： Stephen Felix ,  Daniel Wilkinson ,  Graham Bernard Cunningham

IPC: G06F11/00 ,  G06F11/10 ,  H03K19/21 ,  G06F11/07

Abstract: Signature generation circuitry is configured to update a signature in response to each of a plurality of writes to memory. The signature is updated by performing bitwise operations between current bit values of the signature and at least some of the bits written to memory in response a write. The bitwise operation are order-independent such that the resulting signature is the same irrespective of the order in which the writes are used to update the signature. The signatures are formed in an order-independent manner such that, if no errors have occurred in generating the data to be written to be memory, the signatures will match. In this way, a compact signature is developed that is suitable export from the data processing device for checking against a corresponding data processing device of a machine running a duplicate application.

公开(公告)号：US10817444B2

公开(公告)日：2020-10-27

申请号：US16525833

申请日：2019-07-30

Applicant: Graphcore Limited

Inventor： Daniel John Pelham Wilkinson ,  Richard Luke Southwell Osborne ,  Stephen Felix ,  Graham Bernard Cunningham ,  Alan Graham Alexander

IPC: G06F13/20 ,  G06F13/42 ,  G06F9/00 ,  G06F15/16

Abstract: A system comprising an arrangement of multiple processor modules, and an external interconnect for communicating data in the form of packets to outside the arrangement. The interconnect comprises an exchange block configured to provide flow control. One of the processor modules is arranged to send an exchange request message to the exchange block on behalf of others with data to send outside the arrangement. The exchange block sends an exchange-on message to a first of these processor modules, to cause the first module to start sending packets via the interconnect. Then, once this processor module has sent its last data packet, the exchange block sends an exchange-off message to this processor module to cause it to stop sending packets, and sends another exchange-on message to the next processor module with data to send, and so forth.

公开(公告)号：US12141330B2

公开(公告)日：2024-11-12

申请号：US17374925

申请日：2021-07-13

Applicant: Graphcore Limited

Inventor： Daniel John Pelham Wilkinson ,  Graham Bernard Cunningham ,  Stavros Volos ,  Kapil Vaswani ,  Cedric Alain Marie Fournet ,  Balaji Vembu

IPC: G06F21/72 ,  G06F3/06 ,  G06F21/78 ,  H04L9/06 ,  H04L9/08 ,  H04L9/14 ,  H04L9/32

Abstract: A system and method for encrypting and decrypting data exchanged between a multi-tile processing unit and a storage, where a plurality of keys are used for the encryption. Each of the plurality of keys is associated with a different one or more sets of the processors. Encryption hardware is configured to select a key to use for encryption/decryption operations in dependence upon the set of tiles associated with the data being exchanged. Each write request from a tile contains identifier bits associated with that tile's set of tiles, enabling the encryption hardware to select the key to use for encrypting the data in the write request. Each read completion for a tile contains identifier bits associated with that tile's set of tiles, enabling the encryption hardware to select the key to use for decrypting the data in the read completion.

公开(公告)号：US11615053B2

公开(公告)日：2023-03-28

申请号：US17305682

申请日：2021-07-13

Applicant: Graphcore Limited

Inventor： Daniel John Pelham Wilkinson ,  Lars Paul Huse ,  Richard Luke Southwell Osborne ,  Graham Bernard Cunningham ,  Hachem Yassine

IPC: G06F9/30 ,  G06F15/78 ,  G06F15/82

Abstract: A processor in a network has a plurality of processing units arranged on a chip. An on-chip interconnect enables data to be exchanged between the processing units. A plurality of external interfaces are configured to communicate data off chip in the form of packets, each packet having a destination address identifying a destination of the packet. The external interfaces are connected to respective additional connected processors. A routing bus routes packets between the processing units and the external interfaces. A routing register defines a routing domain for the processor, the routing domain comprising one or more of the additional processor, and at least a subset of further additional processors of the network, wherein the additional processors of the subset are directly or indirectly connected to the processor. The routing domain can be modified by changing the contents of the routing register as a sliding window domain.

公开(公告)号：US20190155768A1

公开(公告)日：2019-05-23

申请号：US16165607

申请日：2018-10-19

Applicant: Graphcore Limited

Inventor： Daniel John Pelham Wilkinson ,  Richard Luke Southwell Osborne ,  Stephen Felix ,  Graham Bernard Cunningham ,  Alan Graham Alexander

IPC: G06F13/20 ,  G06F13/42

Abstract: A processor comprising multiple tiles on the same chip, and an external interconnect for communicating data off-chip in the form of packets. The external interconnect comprises an external exchange block configured to provide flow control and queuing of the packets. One of the tiles is nominated by the compiler to send an external exchange request message to the exchange block on behalf of others with data to send externally. The exchange sends an exchange-on message to a first of these tiles, to cause the first tile to start sending packets via the external interconnect. Then, once this tile has sent its last data packet, the exchange block sends an exchange-off control packet to this tile to cause it to stop sending packets, and sends another exchange-on message to the next tile with data to send, and so forth.