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公开(公告)号:US11482472B2
公开(公告)日:2022-10-25
申请号:US16007260
申请日:2018-06-13
Applicant: Intel Corporation
Inventor: Feras Eid , Adel Elsherbini , Johanna Swan
IPC: H01L23/473 , H01L25/065 , H01L23/31 , H01L23/367 , H01L23/498 , H01L23/467 , H01L23/13 , H01L23/00 , H01L21/48
Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.
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公开(公告)号:US11342243B2
公开(公告)日:2022-05-24
申请号:US16141734
申请日:2018-09-25
Applicant: Intel Corporation
Inventor: Feras Eid , Adel Elsherbini , Johanna Swan
IPC: H01L23/473 , H01L23/538 , H01L23/427 , H01L21/48 , H01L23/22
Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and a heat transfer fluid conduit extending through the substrate. In one embodiment, the heat transfer fluid conduit may be lined with a metallization within the substrate. In a further embodiment, the heat transfer fluid conduit may comprise multiple fluid channels for the removal of heat from multiple surfaces of the at least one integrated circuit device. In still a further embodiment, the substrate may include a molded layer, wherein at least one fluid channel is formed in the molded layer.
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公开(公告)号:US11309619B2
公开(公告)日:2022-04-19
申请号:US16327811
申请日:2016-09-23
Applicant: INTEL CORPORATION
Inventor: Sasha Oster , Georgios Dogiamis , Telesphor Kamgaing , Adel Elsherbini , Shawna Liff , Aleksandar Aleksov , Johanna Swan
Abstract: A waveguide coupling system may include at least one waveguide member retention structure disposed on an exterior surface of a semiconductor package. The waveguide member retention structure may be disposed a defined distance or at a defined location with respect to an antenna carried by the semiconductor package. The waveguide member retention structure may engage and guide a waveguide member slidably inserted into the respective waveguide member retention structure. The waveguide member retention structure may position the waveguide member at a defined location with respect to the antenna to maximize the power transfer from the antenna to the waveguide member.
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公开(公告)号:US11226162B2
公开(公告)日:2022-01-18
申请号:US15957431
申请日:2018-04-19
Applicant: Intel Corporation
Inventor: Feras Eid , Adel Elsherbini , Johanna Swan
IPC: H05K7/20 , F28F3/02 , F28F13/00 , H01L23/373 , H01L23/367
Abstract: A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device. The isotropic thermally conductive section(s) allows heat spreading/removal from hotspots or areas with high-power density and the anisotropic thermally conductive section(s) transfers heat away from the at least one integrated circuit device predominately in a single direction with minimum conduction resistance in areas with uniform power density distribution, while reducing heat transfer in the other directions, thereby reducing thermal cross-talk.
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公开(公告)号:US20210398922A1
公开(公告)日:2021-12-23
申请号:US16909258
申请日:2020-06-23
Applicant: Intel Corporation
Inventor: Georgios Dogiamis , Feras Eid , Adel Elsherbini
IPC: H01L23/66 , H01L23/00 , H01L23/367 , H01L23/498 , H01L23/544 , H01P3/06 , H01L21/48 , H01P11/00
Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.
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公开(公告)号:US20210375820A1
公开(公告)日:2021-12-02
申请号:US16887126
申请日:2020-05-29
Applicant: Intel Corporation
Inventor: Feras Eid , Adel Elsherbini , Georgios Dogiamis
IPC: H01L23/00
Abstract: Magnetic structures may be incorporated into integrated circuit assemblies, which will enable local heating and reflow of solder interconnects for the attachment of integrated circuit devices to electronic substrates. Such magnetic structures will eliminate exposure of the entire integrated circuit assembly to elevated temperatures for an extended period of time, which eliminates associated warpage and thermal degradation consequences from such exposure. Additionally, such magnetic structures will allow for re-workability of specific solder interconnects.
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公开(公告)号:US20210280492A1
公开(公告)日:2021-09-09
申请号:US17318887
申请日:2021-05-12
Applicant: Intel Corporation
Inventor: Shawna Liff , Adel Elsherbini , Johanna Swan , Jimin Yao , Veronica Strong
IPC: H01L23/373 , H01L21/768 , H01L25/065 , H01L23/48
Abstract: A heat spreading material is integrated into a composite die structure including a first IC die having a first dielectric material and a first electrical interconnect structure, and a second IC die having a second dielectric material and a second electrical interconnect structure. The composite die structure may include a composite electrical interconnect structure comprising the first interconnect structure in direct contact with the second interconnect structure at a bond interface. The heat spreading material may be within at least a portion of a dielectric area through which the bond interface extends. The heat spreading material may be located within one or more dielectric materials surrounding the composite interconnect structure, and direct a flow of heat generated by one or more of the first and second IC dies.
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公开(公告)号:US20210159179A1
公开(公告)日:2021-05-27
申请号:US16698557
申请日:2019-11-27
Applicant: Intel Corporation
Inventor: Adel Elsherbini , Shawna Liff , Johanna Swan , Gerald Pasdast
IPC: H01L23/538 , H01L21/304 , H01L21/48 , H01L23/00
Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.
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公开(公告)号:US20210098407A1
公开(公告)日:2021-04-01
申请号:US16586158
申请日:2019-09-27
Applicant: Intel Corporation
Inventor: Adel Elsherbini , Patrick Morrow , Johanna Swan , Shawna Liff , Mauro Kobrinksy , Van Le , Gerald Pasdast
IPC: H01L23/00 , H01L23/48 , H01L23/528 , H01L23/522 , H01L25/18 , H01L25/00 , H01L21/768 , H01L21/82
Abstract: A composite integrated circuit (IC) device structure comprising a host chip and a chiplet. The host chip comprises a first device layer and a first metallization layer. The chiplet comprises a second device layer and a second metallization layer that is interconnected to transistors of the second device layer. A top metallization layer comprising a plurality of first level interconnect (FLI) interfaces is over the chiplet and host chip. The chiplet is embedded between a first region of the first device layer and the top metallization layer. The first region of the first device layer is interconnected to the top metallization layer by one or more conductive vias extending through the second device layer or adjacent to an edge sidewall of the chiplet.
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公开(公告)号:US20200098668A1
公开(公告)日:2020-03-26
申请号:US16141734
申请日:2018-09-25
Applicant: Intel Corporation
Inventor: Feras Eid , Adel Elsherbini , Johanna Swan
IPC: H01L23/473 , H01L23/538 , H01L21/48 , H01L23/427
Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and a heat transfer fluid conduit extending through the substrate. In one embodiment, the heat transfer fluid conduit may be lined with a metallization within the substrate. In a further embodiment, the heat transfer fluid conduit may comprise multiple fluid channels for the removal of heat from multiple surfaces of the at least one integrated circuit device. In still a further embodiment, the substrate may include a molded layer, wherein at least one fluid channel is formed in the molded layer.
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