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公开(公告)号:US20170153687A1
公开(公告)日:2017-06-01
申请号:US15074774
申请日:2016-03-18
Applicant: Intel Corporation
Inventor: Zhenyu Zhu , Anoop Mukker , Daniel Nemiroff , Nobuyuki Suzuki , David W. Vogel
CPC classification number: G06F1/3234 , G06F1/266 , G06F1/3206 , G06F1/325 , Y02D50/20
Abstract: An example method for power management of a user interface includes initiating a low power entry at a data lane of the user interface. The method further includes coordinating with a peripheral device to enter into an ultra-low power state. The peripheral device is to initiate a low power entry at the clock lane to enter the user interface into an ultra-low power state in response to detecting the low power entry at the data lane.
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公开(公告)号:US09465933B2
公开(公告)日:2016-10-11
申请号:US13690111
申请日:2012-11-30
Applicant: Intel Corporation
Inventor: Siddhartha Chhabra , Reshma Lal , Jason Martin , Daniel Nemiroff
Abstract: Embodiments of an invention for virtualizing a hardware monotonic counter are disclosed. In one embodiment, an apparatus includes a hardware monotonic counter, virtualization logic, a first non-volatile storage location, and a second non-volatile storage location. The virtualization logic is to create a virtual monotonic counter from the hardware monotonic counter. The first non-volatile storage location is to store an indicator that the count of the hardware monotonic counter has changed. The second non-volatile storage location is to store an indicator that the count of the virtual monotonic counter has changed.
Abstract translation: 公开了用于虚拟化硬件单调计数器的发明的实施例。 在一个实施例中,装置包括硬件单调计数器,虚拟化逻辑,第一非易失性存储位置和第二非易失性存储位置。 虚拟化逻辑是从硬件单调计数器创建一个虚拟单调计数器。 第一个非易失性存储位置是存储硬件单调计数器的计数改变的指示符。 第二非易失性存储位置是存储虚拟单调计数器的计数改变的指示符。
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公开(公告)号:US12243611B2
公开(公告)日:2025-03-04
申请号:US17856897
申请日:2022-07-01
Applicant: Intel Corporation
Inventor: Minki Cho , Daniel Nemiroff , Carlos Tokunaga , James W. Tschanz , Kah Meng Yeem , Yaxin Shui
IPC: G11C5/00
Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.
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公开(公告)号:US11018863B2
公开(公告)日:2021-05-25
申请号:US16435083
申请日:2019-06-07
Applicant: Intel Corporation
Inventor: Balaji Vembu , Vidhya Krishnan , Sandeep S. Sodhi , Scott Janus , Daniel Nemiroff
Abstract: An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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公开(公告)号:US10582256B2
公开(公告)日:2020-03-03
申请号:US15994751
申请日:2018-05-31
Applicant: INTEL CORPORATION
Inventor: Ramesh Pendakur , Walter C. Gintz , Daniel Nemiroff , Mousumi M. Hazra
IPC: H04N21/4367 , G06F21/72 , G06F21/10 , G06F21/12 , H04L9/32 , H04N21/4363 , H04N21/4408 , H04N21/6334 , H04N21/418
Abstract: A system architecture provides a hardware-based root of trust solution for supporting distribution and playback of premium digital content. In an embodiment, hardware root of trust for digital content and services is a solution where the basis of trust for security purposes is rooted in hardware and firmware mechanisms in a client computing system, rather than in software. From this root of trust, the client computing system constructs an entire media processing pipeline that is protected for content authorization and playback. In embodiments of the present invention, the security of the client computing system for content processing is not dependent on the operating system (OS), basic input/output system (BIOS), media player application, or other host software.
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公开(公告)号:US10367639B2
公开(公告)日:2019-07-30
申请号:US15394324
申请日:2016-12-29
Applicant: Intel Corporation
Inventor: Balaji Vembu , Vidhya Krishnan , Sandeep S. Sodhi , Scott Janus , Daniel Nemiroff
Abstract: An embodiment of a graphics apparatus may include a graphics processor including a kernel executor, and a security engine communicatively coupled to the graphics processor. The security engine may be configured to create a kernel security key, encrypt an executable kernel for the kernel executor in accordance with the kernel security key, and share the kernel security key with the graphics processor.
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公开(公告)号:US20190007209A1
公开(公告)日:2019-01-03
申请号:US15640118
申请日:2017-06-30
Applicant: Intel Corporation
Inventor: Xiaoyu Ruan , Vincent Von Bokern , Daniel Nemiroff
Abstract: Technologies for provisioning cryptographic keys include hardcoding identical cryptographic key components of a Rivest-Shamir-Adleman (RSA) public-private key pair to each compute device of a plurality of compute devices. A unique cryptographic exponent that forms a valid RSA public-private key pair with cryptographic key components hardcoded into each compute device is provided to each compute device so that each compute device has a unique public key. The public key of each compute device may be used to provision unique secrets to the corresponding compute device.
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公开(公告)号:US10168760B2
公开(公告)日:2019-01-01
申请号:US15074774
申请日:2016-03-18
Applicant: Intel Corporation
Inventor: Zhenyu Zhu , Anoop Mukker , Daniel Nemiroff , Nobuyuki Suzuki , David W. Vogel
Abstract: An example method for power management of a user interface includes initiating a low power entry at a data lane of the user interface. The method further includes coordinating with a peripheral device to enter into an ultra-low power state. The peripheral device is to initiate a low power entry at the clock lane to enter the user interface into an ultra-low power state in response to detecting the low power entry at the data lane.
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公开(公告)号:US20180365069A1
公开(公告)日:2018-12-20
申请号:US15622113
申请日:2017-06-14
Applicant: Intel Corporation
Inventor: Daniel Nemiroff , Jason W. Brandt
Abstract: In one embodiment, an apparatus comprises a first processor to generate a first cryptographic key in response to a request from a software application; receive a second cryptographic key generated by a second processor; encrypt the first cryptographic key using the second cryptographic key; and provide the encrypted first cryptographic key for use by the software application.
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公开(公告)号:US20160283721A1
公开(公告)日:2016-09-29
申请号:US15179665
申请日:2016-06-10
Applicant: Intel Corporation
Inventor: Daniel Nemiroff , Paul J. Thadikaran , Andrew H. Gafken , Purushottam Goel , Nicholas D. Triantafillou , Paritosh Saxena , Debra Cablao
CPC classification number: G06F21/577 , G06F9/4401 , G06F21/554 , G06F21/561 , G06F21/575 , G06F21/6218 , G06F21/64 , G06F2221/033 , H04L9/3247
Abstract: Embodiments of techniques and systems for out-of-band verification of host OS components are described. In embodiments, a out-of-band host OS boot sequence verification system (“BSVS”) may access system memory without detection by a host OS process, or “out of band.” The BSVS may access host OS components in the system memory and may generate signatures from memory footprints of the host OS components. These signatures may then be compared to trusted signatures to verify integrity of the host OS components. In embodiments, this verification may be performed during a boot of a host OS or on demand. In embodiments, the trusted signatures may be pre-stored by the BSVS before a boot; in some embodiments, the trusted signatures may be previously-computed and then stored by the BSVS. Other embodiments may be described and claimed.
Abstract translation: 描述用于主机OS组件的带外验证的技术和系统的实施例。 在实施例中,带外主机OS引导序列验证系统(“BSVS”)可以在主机OS进程或“带外”检测的情况下访问系统存储器.BSVS可以访问系统存储器中的主机OS组件 并且可以从主机OS组件的内存覆盖区生成签名。 然后可以将这些签名与可信签名进行比较以验证主机OS组件的完整性。 在实施例中,可以在主机OS的引导期间或者根据需要执行该验证。 在实施例中,信任签名可以在引导之前被BSVS预先存储; 在一些实施例中,可信任签名可以被预先计算,然后由BSVS存储。 可以描述和要求保护其他实施例。
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