公开(公告)号：US20180328957A1

公开(公告)日：2018-11-15

申请号：US15771869

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Feras EID ,  Henning BRAUNISCH ,  Georgios C. DOGIAMIS ,  Sasha N. OSTER

IPC: G01P15/097 ,  B81B7/00 ,  B81C1/00 ,  G01P15/08

CPC classification number: G01P15/097 ,  B81B7/0006 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/0118 ,  B81B2203/04 ,  B81B2203/053 ,  B81B2207/012 ,  B81B2207/07 ,  B81C1/00166 ,  B81C1/0023 ,  G01P15/0802

Abstract: Embodiments of the invention include a microelectronic device having a sensing device and methods of forming the sensing device. In an embodiment, the sensing device includes a mass and a plurality of beams to suspend the mass. Each beam comprises first and second conductive layers and an insulating layer positioned between the first and second conductive layers to electrically isolate the first and second conductive layers. The first conductive layer is associated with drive signals and the second conductive layer is associated with sense signals of the sensing device.

公开(公告)号：US20180286687A1

公开(公告)日：2018-10-04

申请号：US15476842

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Sasha N. OSTER ,  Fay HUA ,  Telesphor KAMGAING ,  Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Johanna M. SWAN

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/033 ,  G03F7/16 ,  B82Y40/00

CPC classification number: H01L21/28562 ,  B82Y40/00 ,  H01L21/033 ,  H01L21/76822 ,  H01L21/76834

Abstract: Embodiments include devices and methods, including a method for processing a substrate. The method includes providing a substrate including a first portion and a second portion, the first portion including a feature, the feature including an electrically conductive region, the second portion including a dielectric surface region. The method also includes performing self-assembled monolayer (SAM) assisted structuring plating to form a structure comprising a metal on the dielectric surface region, the feature being formed using a process other than the SAM assisted structuring plating used to form the structure, and the structure being formed after the feature. Other embodiments are described and claimed.

公开(公告)号：US20180226310A1

公开(公告)日：2018-08-09

申请号：US15748138

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Feras EID ,  Adel A. ELSHERBINI ,  Henning BRAUNISCH ,  Yidnekachew MEKONNEN ,  Krishna BHARATH ,  Mathew J. MANUSHAROW ,  Aleksandar ALEKSOV ,  Nathan FRITZ

IPC: H01L23/14 ,  H01L21/48 ,  H01L23/473 ,  H01L23/538 ,  H01L23/492

CPC classification number: H01L23/147 ,  H01L21/486 ,  H01L21/4871 ,  H01L23/12 ,  H01L23/473 ,  H01L23/492 ,  H01L23/5389

Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.

公开(公告)号：US20180145031A1

公开(公告)日：2018-05-24

申请号：US15876080

申请日：2018-01-19

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/00 ,  H01L25/065 ,  H01L21/683

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20240371799A1

公开(公告)日：2024-11-07

申请号：US18143831

申请日：2023-05-05

Applicant: Intel Corporation

Inventor： Aleksander ALEKSOV ,  Henning BRAUNISCH ,  Neelam PRABHU GAUNKAR

IPC: H01L23/64 ,  H01L23/14 ,  H01L23/498

Abstract: Embodiments disclosed herein include package substrates with integrated inductors. In an embodiment, a package substrate comprises a substrate and a via that passes through the substrate. In an embodiment, the via is electrically conductive. In an embodiment, a spacer is provided around the via. In an embodiment, a ring is around the spacer. In an embodiment, the ring comprises a magnetic material.

公开(公告)号：US20220231394A1

公开(公告)日：2022-07-21

申请号：US17714957

申请日：2022-04-06

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Mathew MANUSHAROW ,  Krishna BHARATH ,  Zhichao ZHANG ,  Yidnekachew S. MEKONNEN ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH ,  Feras EID ,  Javier SOTO

IPC: H01P3/08 ,  H01P3/02 ,  H05K1/02 ,  H01P3/06

Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.

公开(公告)号：US20200350303A1

公开(公告)日：2020-11-05

申请号：US16400768

申请日：2019-05-01

Applicant: Intel Corporation

Inventor： Thomas SOUNART ,  Aleksandar ALEKSOV ,  Henning BRAUNISCH

IPC: H01L27/01 ,  H01L23/00 ,  H01L21/47 ,  H01L49/02 ,  H01L23/522

Abstract: Embodiments described herein are directed to a thin film capacitor (TFC) for power delivery that is in situ in a package substrate and techniques of fabricating the TFC. In one example, the TFC includes a first electrode, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. Each of the dielectric layer and the second electrode comprises an opening. Furthermore, the two openings are positioned over one another such that the openings expose a surface of the first electrode. In this example, a first vertical interconnect access (via) is positioned on the exposed surface of the first electrode and a second via is positioned on an exposed surface of the second electrode. The TFC can be positioned in or on a layer of the package substrate close to a component (e.g., a die, a die stack, etc.) on the package substrate that may require a decoupling capacitance.

公开(公告)号：US20200312782A1

公开(公告)日：2020-10-01

申请号：US16651949

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Feras EID ,  Henning BRAUNISCH ,  Shawna M. LIFF ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN

IPC: H01L23/552 ,  H01L21/48 ,  H01L23/04 ,  H01L23/10 ,  H01L23/498 ,  H01L23/00

Abstract: A device package and a method of forming the device package are described. The device package includes a substrate having a ground plane and dies disposed on the substrate. The dies are electrically coupled to the substrate with solder balls or bumps surrounded by an underfill layer. The device package has a mold layer disposed over and around the dies, the underfill layer, and the substrate. The device package further includes an additively manufactured electromagnetic interference (EMI) shield layer disposed on an outer surface of the mold layer. The additively manufactured EMI shield layer is electrically coupled to the ground plane of the substrate. The outer surface of the mold layer may include a topmost surface and one or more sidewalls that are covered with the additively manufactured EMI shield layer. The additively manufactured EMI shield may include a first and second additively manufactured EMI shield layers and an additively manufactured EMI shield frame.

公开(公告)号：US20200075493A1

公开(公告)日：2020-03-05

申请号：US16677533

申请日：2019-11-07

Applicant: Intel Corporation

Inventor： Henning BRAUNISCH ,  Chia-Pin CHIU ,  Aleksandar ALEKSOV ,  Hinmeng AU ,  Stefanie M. LOTZ ,  Johanna M. SWAN ,  Sujit SHARAN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/13

Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).

公开(公告)号：US20190317285A1

公开(公告)日：2019-10-17

申请号：US16473216

申请日：2017-09-12

Applicant: Intel Corporation

Inventor： Shawna M. LIFF ,  Henning BRAUNISCH ,  Timothy A. GOSSELIN ,  Prasanna RAGHAVAN ,  Yikang DENG ,  Zhiguo QIAN

IPC: G02B6/42 ,  F21V8/00 ,  G02B6/293

Abstract: An optoelectronic apparatus is presented. In embodiments, the apparatus may include a package including a substrate with a first side and a second side opposite the first side, wherein the first side comprises a ball grid array (BGA) field. The apparatus may further include one or more integrated circuits (ICs) disposed on the first side of the substrate, inside the BGA field, that thermally interface with a printed circuit board (PCB), to which the package is to be coupled, one or more optical ICs coupled to the second side and communicatively coupled with the one or more ICs via interconnects provided in the substrate, wherein at least one of the optical ICs is at least partially covered by an integrated heat spreader (IHS), to provide dissipation of heat produced by the at least one optical IC.