公开(公告)号：US20190097057A1

公开(公告)日：2019-03-28

申请号：US16203780

申请日：2018-11-29

Applicant: Intel Corporation

Inventor： Neville L. Dias ,  Chia-Hong Jan ,  Walid M. Hafez ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu

IPC: H01L29/78 ,  H01L21/8234 ,  H03D7/16

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.

公开(公告)号：US11791380B2

公开(公告)日：2023-10-17

申请号：US16713670

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Walid M. Hafez ,  Tanuj Trivedi ,  Jeong Dong Kim ,  Ting Chang ,  Babak Fallahazad ,  Hsu-Yu Chang ,  Nidhi Nidhi

IPC: H01L29/06 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/423 ,  B82Y40/00 ,  B82Y10/00

CPC classification number: H01L29/0669 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/785 ,  B82Y10/00 ,  B82Y40/00

Abstract: Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a substrate, and a first transistor of a first conductivity type over the substrate. In an embodiment, the first transistor comprises a first semiconductor channel, and a first gate electrode around the first semiconductor channel. In an embodiment, the semiconductor device further comprises a second transistor of a second conductivity type above the first transistor. The second transistor comprises a second semiconductor channel, and a second gate electrode around the second semiconductor channel. In an embodiment, the second gate electrode and the first gate electrode comprise different materials.

公开(公告)号：US10930729B2

公开(公告)日：2021-02-23

申请号：US16328704

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Rahul Ramaswamy ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L49/02 ,  H01L21/285 ,  H01L21/306 ,  H01L27/06 ,  C23C16/455

Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.

公开(公告)号：US10854757B2

公开(公告)日：2020-12-01

申请号：US16344226

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Hsu-Yu Chang ,  Chia-Hong Jan ,  Walid M. Hafez ,  Neville L. Dias ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423

Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

公开(公告)号：US10761264B2

公开(公告)日：2020-09-01

申请号：US16462077

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Chia-Hong Jan ,  Walid Hafez ,  Neville Dias ,  Hsu-Yu Chang ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: G02B6/122 ,  G02B6/12 ,  G02B6/00 ,  H01P3/16 ,  G02B6/134 ,  G02B6/136

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming electromagnetic waveguides. In an embodiment, the electromagnetic waveguide may include a first semiconductor fin extending up from a substrate and a second semiconductor fin extending up from the substrate. The fins may be bent towards each other so that a centerline of the first semiconductor fin and a centerline of the second semiconductor fin extend from the substrate at a non-orthogonal angle. Accordingly, a cavity may be defined by the first semiconductor fin, the second semiconductor fin, and a top surface of the substrate. Embodiments of the invention may include a metallic layer and a cladding layer lining the surfaces of the cavity. Additional embodiments may include a core formed in the cavity.

公开(公告)号：US10756210B2

公开(公告)日：2020-08-25

申请号：US16317708

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Neville L. Dias ,  Rahul Ramaswamy ,  Roman W. Olac-Vaw ,  Chen-Guan Lee

IPC: H01L51/05 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

公开(公告)号：US10192969B2

公开(公告)日：2019-01-29

申请号：US15327641

申请日：2014-08-19

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid Hafez ,  Hsu-Yu Chang ,  Roman Olac-Vaw ,  Ting Chang ,  Rahul Ramaswamy ,  Pei-Chi Liu ,  Neville Dias

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/3213 ,  H01L23/535 ,  H01L23/66 ,  H01L21/3115

Abstract: Semiconductor device(s) including a transistor with a gate electrode having a work function monotonically graduating across the gate electrode length, and method(s) to fabricate such a device. In embodiments, a gate metal work function is graduated between source and drain edges of the gate electrode for improved high voltage performance. In embodiments, thickness of a gate metal graduates from a non-zero value at the source edge to a greater thickness at the drain edge. In further embodiments, a high voltage transistor with graduated gate metal thickness is integrated with another transistor employing a gate electrode metal of nominal thickness. In embodiments, a method of fabricating a semiconductor device includes graduating a gate metal thickness between a source end and drain end by non-uniformly recessing the first gate metal within the first opening relative to the surrounding dielectric.

公开(公告)号：US09947585B2

公开(公告)日：2018-04-17

申请号：US15127839

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Chia-Hong Jan ,  Roman W. Olac-Vaw ,  Hsu-Yu Chang ,  Neville L. Dias ,  Walid M. Hafez ,  Rahul Ramaswamy

IPC: H01L29/78 ,  H01L29/76 ,  H01L27/088 ,  H01L21/283 ,  H01L21/8234 ,  H01L21/265 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L21/823412 ,  H01L21/26586 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42368 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

Abstract: An embodiment includes an apparatus comprising: a non-planar transistor comprising a fin, the fin including a source region having a source region width and a source region height, a channel region having a channel region width and a channel region height, a drain region having a drain width and a drain height, and a gate dielectric formed on a sidewall of the channel region; wherein the apparatus includes at least one of (a) the channel region width being wider than the source region width, and (b) the gate dielectric including a first gate dielectric thickness at a first location and a second gate dielectric thickness at a second location, the first and second locations located at an equivalent height on the sidewall and the first and second gate dielectrics thicknesses being unequal to one another. Other embodiments are described herein.

公开(公告)号：US20170125419A1

公开(公告)日：2017-05-04

申请号：US15409435

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Chia-Hong Jan ,  Walid M. Hafez ,  Jeng-Ya David Yeh ,  Hsu-Yu Chang ,  Neville L. Dias ,  Chanaka D. Munasinghe

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/2256 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0928 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66803 ,  H01L29/7851

Abstract: An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.

公开(公告)号：US20250113561A1

公开(公告)日：2025-04-03

申请号：US18476624

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Marko Radosavljevic ,  Hsu-Yu Chang ,  Scott M. Mokler ,  Stephanie Chin ,  Walid M. Hafez

IPC: H01L29/06 ,  H01L27/092 ,  H01L29/423 ,  H01L29/778 ,  H01L29/78 ,  H01L29/786

Abstract: In stacked transistor device, such as a complementary field-effect-transistor (CFET) device, different strain materials may be used in different layers, e.g., a tensile material is deposited in a first isolation region in the PMOS layer, and a compressive material is deposited in second isolation region in the NMOS layer. The strain materials may be stacked, such that the second isolation region may be positioned over the first isolation region. In some cases, in one or both of the isolation regions, a liner material is included between the strain material and the source and drain regions. Certain embodiments provide independent tuning of strain forces in a stacked transistor device. Different materials are selected for different layers in the stacked device to provide favorable performance enhancement or tuning (e.g., adjustment of the threshold voltage) in NMOS and PMOS layers.