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    Transistors with metal chalcogenide channel materials
    11.
    发明授权
    Transistors with metal chalcogenide channel materials 有权

    公开(公告)号：US11888034B2

    公开(公告)日：2024-01-30

    申请号：US16435358

    申请日：2019-06-07

    Applicant: Intel Corporation

    Inventor： Abhishek A. Sharma ,  Ashish Agarwal ,  Urusa Alaan ,  Christopher Jezewski ,  Kevin Lin ,  Carl Naylor

    IPC: H01L29/26 ,  H01L29/51 ,  H01L29/16 ,  H01L27/092

    CPC classification number: H01L29/26 ,  H01L27/092 ,  H01L29/16 ,  H01L29/517

    Abstract: Transistor structures employing metal chalcogenide channel materials may be formed where a chalcogen is introduced into at least a portion of a precursor material that comprises reactive metal(s). The precursor material may be substantially metallic, or may be a metallic oxide (e.g., an oxide semiconductor). The metal(s) may be transition, Group II, Group III, Group V elements, or alloys thereof. An oxide of one or more such metals (e.g., IGZO) may be converted into a chalcogenide (e.g., IGZSx or IGZSex) having semiconducting properties. The chalcogenide formed in this manner may be only a few monolayers in thickness (and may be more thermally stable than many oxide semiconductors. Where not all of the precursor material is converted, a transistor structure may retain the precursor material, for example as part of a transistor channel or a gate dielectric. Backend transistors including metal chalcogenide channel materials may be fabricated over silicon CMOS circuitry.

    Metal and spacer patterning for pitch division with multiple line widths and spaces
    12.
    发明授权
    Metal and spacer patterning for pitch division with multiple line widths and spaces 有权

    公开(公告)号：US11710636B2

    公开(公告)日：2023-07-25

    申请号：US16013842

    申请日：2018-06-20

    Applicant: Intel Corporation

    Inventor： Kevin Lin ,  Charles Wallace

    IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/285 ,  H01L21/768

    CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/28556 ,  H01L21/32133 ,  H01L21/768

    Abstract: Metal spacer-based approaches for fabricating conductive lines/interconnects are described. In an example, an integrated circuit structure includes a substrate. A first spacer pattern is on the substrate, the first spacer pattern comprising a first plurality of dielectric spacers and a first plurality of metal spacers formed along sidewalls of the first plurality of dielectric spacers, wherein the first plurality of dielectric spacers have a first width (W1). A second spacer pattern is on the substrate, where the second spacer pattern interleaved with the first spacer pattern, the second spacer pattern comprising a second plurality of dielectric spacers having a second width (W2) formed on exposed sidewalls of the first plurality of metal spacers, and a second plurality of metal spacers formed on exposed sidewalls of the second plurality of dielectric spacers.

    Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias
    15.
    发明授权
    Textile patterning for subtractively-patterned self-aligned interconnects, plugs, and vias 有权

    公开(公告)号：US11276581B2

    公开(公告)日：2022-03-15

    申请号：US16435240

    申请日：2019-06-07

    Applicant: Intel Corporation

    Inventor： Kevin Lin ,  Robert Lindsey Bristol ,  Alan M. Myers

    IPC: H01L21/32 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/033 ,  H01L23/522

    Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

    INTEGRATED CIRCUITS WITH LINE BREAKS AND LINE BRIDGES WITHIN A SINGLE INTERCONNECT LEVEL
    16.
    发明申请
    INTEGRATED CIRCUITS WITH LINE BREAKS AND LINE BRIDGES WITHIN A SINGLE INTERCONNECT LEVEL 有权

    公开(公告)号：US20220076995A1

    公开(公告)日：2022-03-10

    申请号：US17530777

    申请日：2021-11-19

    Applicant: Intel Corporation

    Inventor： Kevin Lin ,  Christopher J. Jezewski

    IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

    Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

    Selective metal removal for conductive interconnects in integrated circuitry
    17.
    发明授权
    Selective metal removal for conductive interconnects in integrated circuitry 有权

    公开(公告)号：US11158515B2

    公开(公告)日：2021-10-26

    申请号：US16334324

    申请日：2016-09-30

    Applicant: Intel Corporation

    Inventor： Kevin Lin ,  Rahim Kasim ,  Manish Chandhok ,  Florian Gstrein

    IPC: H01L21/3213 ,  H01L21/302 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

    Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

    Resonator structure encapsulation
    18.
    发明授权
    Resonator structure encapsulation 有权

    公开(公告)号：US11121691B2

    公开(公告)日：2021-09-14

    申请号：US16348830

    申请日：2016-12-29

    Applicant: Intel Corporation

    Inventor： Kevin Lin ,  Kimin Jun ,  Edris Mohammed

    IPC: H03H3/02 ,  H03H9/17

    Abstract: The RF filters used in conventional mobile devices often include resonator structures, which often require free-standing air-gap structure to prevent mechanical vibrations of the resonator from being damped by a bulk material. A method for fabricating a resonator structure comprises depositing a non-conformal thin-film to the resonator structure to seal air gap cavities in the resonator structure.

    INTEGRATED CIRCUITS WITH LINE BREAKS AND LINE BRIDGES WITHIN A SINGLE INTERCONNECT LEVEL
    20.
    发明申请
    INTEGRATED CIRCUITS WITH LINE BREAKS AND LINE BRIDGES WITHIN A SINGLE INTERCONNECT LEVEL 审中-公开

    公开(公告)号：US20200321246A1

    公开(公告)日：2020-10-08

    申请号：US16651295

    申请日：2017-12-27

    Applicant: Intel Corporation

    Inventor： Kevin Lin ,  Christopher J. Jezewski

    IPC: H01L21/768 ,  H01L21/311 ,  H01L23/528

    Abstract: Integrated circuit (IC) interconnect lines having line breaks and line bridges within one interconnect level that are based on a single lithographic mask pattern. Multi-patterning may be employed to define a grating structure of a desired pitch in a first mask layer. Breaks and bridges between the grating structures may be derived from a second mask layer through a process-based selective occlusion of openings defined in the second mask layer that are below a threshold minimum lateral width. Portions of the grating structure underlying openings defined in the second mask layer that exceed the threshold minimum lateral width are removed. Trenches in an underlayer may then be etched based on a union of the remainder of the grating structure and the occluded openings in the second mask layer. The trenches may then be backfilled to form the interconnect lines.

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