公开(公告)号：US10318295B2

公开(公告)日：2019-06-11

申请号：US14979083

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Christopher J. Hughes

IPC: G06F9/312 ,  G06F9/30 ,  G06F12/0891 ,  G06F9/46 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/0842

Abstract: A processor of an aspect includes a decode unit to decode a transaction end plus commit to persistence instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to atomically ensure that data associated with all prior store to memory operations made to a persistent memory, which are to have been accepted to memory when performance of the instruction begins, but which are not necessarily to have been stored in the persistent memory when the performance of the instruction begins, are to be stored in the persistent memory before the instruction becomes globally visible. The execution unit, in response to the instruction, is also to atomically end a transactional memory transaction before the instruction becomes globally visible.

公开(公告)号：US10303477B2

公开(公告)日：2019-05-28

申请号：US14751892

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Kshitij A. Doshi

IPC: G06F9/30 ,  G06F12/0875 ,  G06F11/14 ,  G06F11/00

Abstract: A processor includes at least one memory controller, and a decode unit to decode a persistent commit demarcate instruction. The persistent commit demarcate instruction is to indicate a destination storage location. The processor also includes an execution unit coupled with the decode unit and the at least one memory controller. The execution unit, in response to the persistent commit demarcate instruction, is to store a demarcation value in the destination storage location. The demarcation value may demarcate at least all first store to persistent memory operations that are to have been accepted to memory when the persistent commit demarcate instruction is performed, but which are not necessarily to have been stored persistently, from at least all second store to persistent memory operations that are not yet to have been accepted to memory when the persistent commit demarcate instruction is performed.

公开(公告)号：US20190004871A1

公开(公告)日：2019-01-03

申请号：US15636119

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi

IPC: G06F9/54

Abstract: A computing apparatus, including: a hardware computing platform; and logic to operate on the hardware computing platform, configured to: receive a microservice instance registration for a microservice accelerator, wherein the registration includes a microservice that the microservice accelerator is configured to provide, and a microservice connection capability indicating an ability of the microservice instance to communicate directly with other instances of the same or a different microservice; and log the registration in a microservice registration database.

公开(公告)号：US20190004862A1

公开(公告)日：2019-01-03

申请号：US15637003

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Andrew J. Herdrich ,  Edwin Verplanke ,  Daniel Rivas Barragan

IPC: G06F9/50

Abstract: Technologies for managing quality of service of a platform interconnect include a compute device. The compute device includes one or more processors, one or more resources capable of being utilized by the one or more processors, and a platform interconnect to facilitate communication of messages between the one or more processors and the one or more resources. The compute device is to obtain class of service data for one or more workloads to be executed by the compute device. The class of service data is indicative of a capacity of one or more of the resources to be utilized in the execution of each corresponding workload. The compute device is also to execute the one or more workloads and manage the amount of traffic transmitted through the platform interconnect for each corresponding workload as a function of the class of service data as the one or more workloads are executed.

公开(公告)号：US20180189177A1

公开(公告)日：2018-07-05

申请号：US15394667

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Mark A. Schmisseur ,  Steen Larsen ,  Chet R. Douglas

IPC: G06F12/06 ,  H04L29/08 ,  G06F12/0802

CPC classification number: G06F12/06 ,  G06F11/1446 ,  G06F12/0802 ,  G06F2212/60 ,  H04L67/06 ,  H04L67/1095 ,  H04L67/2842

Abstract: Apparatus and method for distributed management of data objects in a network of compute nodes are disclosed herein. A first compute node interface may be communicatively coupled to a first compute node to receive a request from the first compute node for at least a portion of a particular version of a data object, wherein the first compute node interface is to include mapping information and logic, wherein the logic is to redirect the request to a second compute node interface associated with a second compute node when the second compute node is mapped to a plurality of data object addresses that includes an address associated with the data object in accordance with the mapping information, and wherein the first compute node is to receive, as a response to the request, the at least a portion of the particular version of the data object from a third compute node interface associated with a third compute node.

公开(公告)号：US09971686B2

公开(公告)日：2018-05-15

申请号：US14628954

申请日：2015-02-23

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Thomas Willhalm

IPC: G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F9/30 ,  G06F12/084

CPC classification number: G06F12/0804 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30192 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/452 ,  G06F2212/621

Abstract: A processor of an aspect includes a plurality of packed data registers, and a decode unit to decode a vector cache line write back instruction. The vector cache line write back instruction is to indicate a source packed memory indices operand that is to include a plurality of memory indices. The processor also includes a cache coherency system coupled with the packed data registers and the decode unit. The cache coherency system, in response to the vector cache line write back instruction, to cause, any dirty cache lines, in any caches in a coherency domain, which are to have stored therein data for any of a plurality of memory addresses that are to be indicated by any of the memory indices of the source packed memory indices operand, to be written back toward one or more memories. Other processors, methods, and systems are also disclosed.

公开(公告)号：US20180077226A1

公开(公告)日：2018-03-15

申请号：US15260638

申请日：2016-09-09

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Kshitij A. Doshi ,  Daniel Rivas Barragan ,  Alejandro Duran Gonzalez

IPC: H04L29/08 ,  H04L12/933

CPC classification number: H04L49/15 ,  H04L29/10

Abstract: Technologies for performing switch-based collective operations in a fabric architecture include a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to identify sub-operations of a collective operation of a collective operation request received from one of the computing nodes and identify a plurality of operands for each of the sub-operations. The network switch is additionally configured to request a value for each of the operands from a corresponding target computing node at which the respective value is stored, determine a result of the collective operation as a function of the requested operand values, and transmit the result to the requesting computing node. Other embodiments are described herein.

公开(公告)号：US20170185413A1

公开(公告)日：2017-06-29

申请号：US14998151

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Kshitij A. Doshi ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal ,  Deborah T. Marr

IPC: G06F9/38 ,  G06F15/80 ,  G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30098

Abstract: Single Instruction, Multiple Data (SIMD) technologies are described. A processer may include a first register to receive a plurality of source elements and second register. The processor may receive a permute index at a third register. The conjugate permute index has elements, each of which corresponds to one of the source elements. The processor then stores each of the source elements to a position in the second register based on a select element corresponding to the source element.

公开(公告)号：US20170177365A1

公开(公告)日：2017-06-22

申请号：US14979083

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Christopher J. Hughes

IPC: G06F9/30 ,  G06F12/10 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/30101 ,  G06F9/3016 ,  G06F9/467 ,  G06F12/0842 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/1027

Abstract: A processor of an aspect includes a decode unit to decode a transaction end plus commit to persistence instruction. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the instruction, is to atomically ensure that all prior store to memory operations made to a persistent memory, which are to have been accepted to memory when performance of the instruction begins, but which are not necessarily to have been stored in the persistent memory when the performance of the instruction begins, are to be stored in the persistent memory before the instruction becomes globally visible. The execution unit, in response to the instruction, is also to atomically end a transactional memory transaction before the instruction becomes globally visible.

公开(公告)号：US20160321185A1

公开(公告)日：2016-11-03

申请号：US14697832

申请日：2015-04-28

Applicant: Intel Corporation

Inventor： Kshitij A. Doshi ,  Christopher J. Hughes

IPC: G06F12/08 ,  G06F3/06

Abstract: In one embodiment, a processor includes a control logic to determine whether to enable an incoming data block associated with a first priority to displace, in a cache memory coupled to the processor, a candidate victim data block associated with a second priority and stored in the cache memory, based at least in part on the first and second priorities, a first access history associated with the incoming data block and a second access history associated with the candidate victim data block. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括控制逻辑，以确定是否使与第一优先级相关联的传入数据块能够在耦合到处理器的高速缓冲存储器中移位与第二优先级相关联并存储在第二优先级中的候选受害者数据块 至少部分地基于第一和第二优先级，与输入数据块相关联的第一访问历史和与候选受害者数据块相关联的第二访问历史。 描述和要求保护其他实施例。