公开(公告)号：US09972601B2

公开(公告)日：2018-05-15

申请号：US14768209

申请日：2014-09-26

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/49 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/207

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US20160276311A1

公开(公告)日：2016-09-22

申请号：US14768209

申请日：2014-08-26

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/528 ,  H01L25/00 ,  H01L23/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/481 ,  H01L23/49 ,  H01L23/528 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/96 ,  H01L25/07 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48235 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06548 ,  H01L2225/06575 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装，其包括至少部分地嵌入第一封装层中的第一裸片和至少部分地嵌入第二封装层中的第二裸片。 第一管芯可以具有设置在第一封装层的第一侧的第一多个管芯级互连结构。 IC封装还可以包括至少部分地嵌入在第一封装层中并被配置为在第一封装层的第一和第二侧之间路由电信号的多个电路由特征。 第二侧可以布置成与第一侧相对。 第二管芯可以具有第二多个管芯级互连结构，其可以通过接合引线与多个电路径特征的至少一个子集电耦合。

公开(公告)号：US09373588B2

公开(公告)日：2016-06-21

申请号：US14034854

申请日：2013-09-24

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf ,  Wolfgang Molzer ,  Bernd Memmler ,  Edmund Goetz ,  Hans-Joachim Barth ,  Sven Albers ,  Thorsten Meyer

IPC: H01L29/40 ,  H01L23/538 ,  H01L21/768 ,  H01L23/522 ,  H01L23/00 ,  H01L25/07 ,  H01L25/00 ,  H01L25/065 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

Abstract translation: 本说明书的实施例包括嵌入在微电子衬底中的堆叠微电子骰子及其制造方法。 在一个实施例中，至少一个第一微电子管芯连接到第二微电子管芯，其中在第二微电子管芯和至少一个第一微电子管芯之间提供底部填充材料。 然后通过将第一微电子管芯和第二微电子管芯层压在衬底材料中来形成微电子衬底。

公开(公告)号：US11250981B2

公开(公告)日：2022-02-15

申请号：US16993152

申请日：2020-08-13

Applicant: Intel Corporation

Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

IPC: H01L23/64 ,  H01F17/00 ,  H01F41/04 ,  H01L23/522 ,  H01L23/00 ,  H01F27/28

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US10522454B2

公开(公告)日：2019-12-31

申请号：US15997555

申请日：2018-06-04

Applicant: Intel Corporation

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Andreas Wolter ,  Georg Seidemann ,  Sven Albers ,  Christian Geissler

IPC: H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L25/16 ,  H01L23/13

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

公开(公告)号：US20170103956A1

公开(公告)日：2017-04-13

申请号：US15294499

申请日：2016-10-14

Applicant: Intel Corporation

Inventor： Thorsten Meyer ,  Gerald Ofner ,  Teodora Ossiander ,  Frank Zudock ,  Christian Geissler

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L24/11 ,  H01L21/02282 ,  H01L21/02318 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/7685 ,  H01L21/76871 ,  H01L23/525 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/81 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0361 ,  H01L2224/0381 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05083 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/211 ,  H01L2224/8112 ,  H01L2224/81191 ,  H01L2224/81801 ,  H01L2224/821 ,  H01L2224/82105 ,  H01L2224/94 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/143 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2224/03

Abstract: Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.

公开(公告)号：US20160148920A1

公开(公告)日：2016-05-26

申请号：US15009731

申请日：2016-01-28

Applicant: Intel Corporation

Inventor： Reinhard Mahnkopf ,  Wolfgang Molzer ,  Bernd Memmler ,  Edmund Goetz ,  Hans-Joachim Barth ,  Sven Albers ,  Thorsten Meyer

IPC: H01L25/00 ,  H01L21/768 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/5226 ,  H01L23/5384 ,  H01L23/562 ,  H01L24/03 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/16148 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Embodiments of the present description include stacked microelectronic dice embedded in a microelectronic substrate and methods of fabricating the same. In one embodiment, at least one first microelectronic die is attached to a second microelectronic die, wherein an underfill material is provided between the second microelectronic die and the at least one first microelectronic die. The microelectronic substrate is then formed by laminating the first microelectronic die and the second microelectronic die in a substrate material.

公开(公告)号：US20250167180A1

公开(公告)日：2025-05-22

申请号：US19033078

申请日：2025-01-21

Applicant: Intel Corporation

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/49 ,  H01L23/528 ,  H01L25/00 ,  H01L25/07

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

公开(公告)号：US11984246B2

公开(公告)日：2024-05-14

申请号：US17566529

申请日：2021-12-30

Applicant: Intel Corporation

Inventor： Andreas Wolter ,  Thorsten Meyer ,  Gerhard Knoblinger

IPC: H01F17/00 ,  H01F41/04 ,  H01L23/00 ,  H01L23/522 ,  H01L23/64 ,  H01F27/28

CPC classification number: H01F17/0033 ,  H01F41/046 ,  H01L23/5227 ,  H01L23/645 ,  H01L24/17 ,  H01F2017/0086 ,  H01F2027/2814 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0401 ,  H01L2224/05647 ,  H01L2224/11 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/11462 ,  H01L2224/16265 ,  H01L2224/16267 ,  H01L2224/1703 ,  H01L2224/171 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2224/0345 ,  H01L2924/00014 ,  H01L2224/03462 ,  H01L2924/00014 ,  H01L2224/03464 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2224/11462 ,  H01L2924/00014 ,  H01L2224/1132 ,  H01L2924/00014 ,  H01L2224/11334 ,  H01L2924/00014

Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.

公开(公告)号：US10249598B2

公开(公告)日：2019-04-02

申请号：US15915769

申请日：2018-03-08

Applicant: INTEL CORPORATION

Inventor： Thorsten Meyer ,  Pauli Jaervinen ,  Richard Patten

IPC: H01L25/065 ,  H01L23/49 ,  H01L25/07 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/528 ,  H01L25/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.