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公开(公告)号:US11099966B2
公开(公告)日:2021-08-24
申请号:US16738311
申请日:2020-01-09
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Matthias Klein , Deanna P. D. Berger , Craig R. Walters
Abstract: Aspects of the invention include efficient generation of instrumentation data for direct memory access operations. A non-limiting example apparatus includes an instrumentation component, residing in a cache in communication with a plurality of processing units, an accelerator, and a plurality of input output interfaces. The cache includes a direct memory access monitor that receives events from the accelerator its respective I/O interface and stores DMA state and latency for each event. The cache also includes a bucket including a DMA counter and a latency counter in communication with the DMA monitor, wherein the bucket stores in the DMA counter a count of DMAs coming from a source and stores in the latency counter the latency measured for each DMA coming from the source.
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公开(公告)号:US20210224073A1
公开(公告)日:2021-07-22
申请号:US17224198
申请日:2021-04-07
Applicant: International Business Machines Corporation
Inventor: Louis P. Gomes , Bruce Giamei , Timothy Slegel , Mark Farrell , Matthias Klein
Abstract: A method is provided that is executable by a processor of a computer. Note that the processor is communicatively coupled to a memory of the computer, and the memory stores a response block of a call command. In implementing the method, the processor defines a sub-functions field in the response block of the call command. Further the processor indicates that a set of functions of a set of instructions are installed and available at an interface based on a corresponding sub-functions flag within the sub-functions field being set. Note that the interface is also being executed on the computer and that the set of functions being represented by the corresponding sub-functions flag. The processor further indicates that the set of functions of the set of instructions are not installed based on the corresponding sub-functions flag not being set.
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13.
公开(公告)号:US20200272528A1
公开(公告)日:2020-08-27
申请号:US16286987
申请日:2019-02-27
Applicant: International Business Machines Corporation
Inventor: Matthias Klein , Simon Weishaupt , Anthony Thomas Sofia , Jonathan D. Bradbury , Mark S. Farrell , Mahmoud Amin , Timothy Slegel
Abstract: A method is provided that includes receiving, by a firmware from an originating software, an asynchronous request for an instruction of an algorithm for compression of data. The firmware operates on a first processor and the originating software operates on a second processor. The firmware issues a synchronous request to the first processor to cause the processor to execute the instruction synchronously. It is determined, by the firmware, whether an interrupt is received from the first processor with respect to the first processor executing the instruction. The firmware retries the issuance of the synchronous request each time the interrupt is received until a retry threshold is reached.
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公开(公告)号:US20200272476A1
公开(公告)日:2020-08-27
申请号:US16286985
申请日:2019-02-27
Applicant: International Business Machines Corporation
Inventor: Louis P. Gomes , Bruce Giamei , Timothy Slegel , Mark Farrell , Matthias Klein
Abstract: A method is provided that is executable by a processor of a computer. Note that the processor is communicatively coupled to a memory of the computer, and the memory stores a response block of a call command. In implementing the method, the processor defines a sub-functions field in the response block of the call command. Further the processor indicates that a set of functions of a set of instructions are installed and available at an interface based on a corresponding sub-functions flag within the sub-functions field being set. Note that the interface is also being executed on the computer and that the set of functions being represented by the corresponding sub-functions flag. The processor further indicates that the set of functions of the set of instructions are not installed based on the corresponding sub-functions flag not being set.
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公开(公告)号:US10666289B1
公开(公告)日:2020-05-26
申请号:US16249029
申请日:2019-01-16
Applicant: International Business Machines Corporation
Inventor: Anthony Thomas Sofia , Brad Stilwell , Matthias Klein
IPC: H03M7/40
Abstract: Embodiments of the present invention are directed to a computer-implemented method for data compression. The method includes monitoring data, from a data stream, stored in an input buffer and system memory of a data compression system. The method further includes choosing an encoding scheme based in part upon the amount of data in the input buffer. The method further includes encoding data using the encoding scheme to compress the data from the data stream. The method further includes reevaluating, during the data stream, an encoding scheme choice based in part upon the amount of data in the input buffer.
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公开(公告)号:US10601441B2
公开(公告)日:2020-03-24
申请号:US16358764
申请日:2019-03-20
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Anthony T. Sofia , Jonathan D. Bradbury , Matthias Klein , Bruce Giamei
Abstract: Systems, methods, and computer-readable media are described for performing data compression in a manner that does not require software to make a call to hardware to close a compressed data block, thereby reducing computational overhead. In response to a request from software to data compression hardware for a data encoding, the hardware may return the data encoding as well as an end-of-block symbol encoding value and bit length. The hardware may load the end-of-block symbol encoding value and bit length into a different area in the returned structure such that the software has direct access to the value. When the software determines that a block should be closed, the software may retrieve the end-of-block symbol and insert it into the block without needing to make a call to hardware. The software may then make a call to the hardware to request a new data encoding for subsequent compressed data blocks.
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17.
公开(公告)号:US20200081627A1
公开(公告)日:2020-03-12
申请号:US16682481
申请日:2019-11-13
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Edward W. Chencinski , Bruce Ratcliff , Eric N. Lais , Michael James Becht , Matthias Klein
Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.
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公开(公告)号:US20200067523A1
公开(公告)日:2020-02-27
申请号:US16668061
申请日:2019-10-30
Applicant: International Business Machines Corporation
Inventor: Anthony T. Sofia , Matthias Klein , Jonathan D. Bradbury , Peter Sutton
IPC: H03M7/30 , G06F9/38 , G06F15/173
Abstract: A computer system includes a plurality of hardware processors, and a hardware accelerator. A first processor among the plurality of processor runs an application that issues a data compression request to compress or decompress a data stream. The hardware accelerator selectively operates in different modes to compresses or decompresses the data stream. Based on a selected mode, the hardware accelerator can utilize a different number of processors among the plurality of hardware to compress or decompress the data stream.
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公开(公告)号:US20200004433A1
公开(公告)日:2020-01-02
申请号:US16025448
申请日:2018-07-02
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Edward W. Chencinski , Bruce Ratcliff , Eric N. Lais , Michael James Becht , Matthias Klein
Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.
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公开(公告)号:US10447296B1
公开(公告)日:2019-10-15
申请号:US16015692
申请日:2018-06-22
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor: Anthony T. Sofia , Matthias Klein , Peter G. Sutton
Abstract: A computer system includes a hardware controller and an internal millicode storage area. The controller includes an accelerator that decompresses a data stream requested by an application. The internal millicode storage area can store a compression dictionary library including a plurality of different pre-defined compression dictionaries. A host system includes a dictionary manager that determines a compression dictionary from the plurality of different pre-defined compression dictionaries included in the dictionary library to decompress the data stream. The accelerator can access the internal millicode storage area to obtain the determined compression dictionary, and to decompress the data stream according to the determined compression dictionary.
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