公开(公告)号：US10354946B2

公开(公告)日：2019-07-16

申请号：US15945913

申请日：2018-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H01L23/49 ,  H01L23/498 ,  H01L25/065 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/18 ,  H05K3/34 ,  H05K3/46 ,  H01L25/00

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

公开(公告)号：US10145892B2

公开(公告)日：2018-12-04

申请号：US15243375

申请日：2016-08-22

Applicant: International Business Machines Corporation

Inventor： Robert L. Franch ,  Phillip J. Restle ,  Thomas Strach ,  Christos Vezyrtzis ,  Scott F. Warnock

IPC: G01R31/28

Abstract: A method for increasing a resolution of an on-chip measurement circuit is provided. The method includes propagating a first signal through the on-chip measurement circuit to generate a first output. The method also includes propagating a second signal through the on-chip measurement circuit to generate a second output. The second signal includes a delay. The method also includes reconciling the first output and the second output to determine the resolution of the on-chip measurement circuit. The resolution of the on-chip measurement circuit increases in correspondence with a fineness of a step of the delay.

公开(公告)号：US09684759B2

公开(公告)日：2017-06-20

申请号：US14925097

申请日：2015-10-28

Applicant: International Business Machines Corporation

Inventor： Harry Barowski ,  Joachim Keinert ,  Sourav Saha ,  Thomas Strach

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/82 ,  G06F2217/84

Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

公开(公告)号：US10734317B2

公开(公告)日：2020-08-04

申请号：US16438736

申请日：2019-06-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H01L23/49 ,  H01L23/498 ,  H01L25/065 ,  H01L25/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K3/18 ,  H05K3/34 ,  H05K3/46

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

公开(公告)号：US20200033927A1

公开(公告)日：2020-01-30

申请号：US16595549

申请日：2019-10-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Preetham M. Lobo ,  Thomas Strach ,  Tobias Webel

IPC: G06F1/28 ,  G06F1/324 ,  G06F1/3206 ,  G06F1/26

Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.

公开(公告)号：US10149388B2

公开(公告)日：2018-12-04

申请号：US15175378

申请日：2016-06-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce J. Chamberlin ,  Andreas Huber ,  Harald Huels ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H05K1/18 ,  H05K3/34 ,  H05K3/00 ,  B23K1/00 ,  H05K1/02 ,  H05K1/09 ,  H05K1/11 ,  H05K3/46 ,  H05K1/16 ,  H05K3/42

Abstract: A method for embedding a discrete electrical device in a printed circuit board (PCB) is provided, which includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to a conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first device contact and the conductive structure in the first layer; and establishing a second electrical connection between a second device contact and a second layer, the second layer being one of the conductive layers of a second horizontal core section.

公开(公告)号：US09980385B2

公开(公告)日：2018-05-22

申请号：US15494672

申请日：2017-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

IPC: H05K1/18 ,  H05K1/14 ,  H05K3/46 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11 ,  H05K3/34 ,  H05K1/02

CPC classification number: H05K1/183 ,  H01L23/49838 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06537 ,  H01L2225/06548 ,  H05K1/0219 ,  H05K1/115 ,  H05K1/144 ,  H05K1/181 ,  H05K3/0097 ,  H05K3/18 ,  H05K3/34 ,  H05K3/4697 ,  H05K2201/049 ,  H05K2201/10015 ,  H05K2201/10106

Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

公开(公告)号：US09146772B2

公开(公告)日：2015-09-29

申请号：US14057984

申请日：2013-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lee E. Eisen ,  Michael S. Floyd ,  Thomas Strach ,  Huajun Wen ,  Tingdong Zhou

IPC: G06F1/26 ,  G06F1/32 ,  G06F9/46 ,  G06F11/30

CPC classification number: G06F9/46 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3243 ,  G06F1/329 ,  G06F11/3024 ,  G06F2201/86 ,  Y02D10/24

Abstract: In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

公开(公告)号：US11586267B2

公开(公告)日：2023-02-21

申请号：US16225301

申请日：2018-12-19

Applicant: International Business Machines Corporation

Inventor： Thomas Strach ,  Preetham M. Lobo ,  Tobias Webel

IPC: G06F1/3206 ,  G06F1/3287 ,  H02H1/06 ,  H02H3/247 ,  G01R19/165

Abstract: Embodiments of the present disclosure relate to managing power provided to a semiconductor circuit to prevent undervoltage conditions. A measured voltage value describing a measured supply voltage at a first subcircuit of a semiconductor circuit can be received, the measured voltage value having a first resolution. A selected metric indicative of a supply voltage present at the first subcircuit can be received, the selected metric having a second resolution higher than the first resolution. The selected metric is calibrated to obtain a calibrated metric when a transition of the measured voltage value occurs.

公开(公告)号：US20180088650A1

公开(公告)日：2018-03-29

申请号：US15356804

申请日：2016-11-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Preetham M. Lobo ,  Thomas Strach ,  Tobias Webel

IPC: G06F1/28 ,  G06F1/26

CPC classification number: G06F1/28 ,  G06F1/266 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126

Abstract: A semiconductor circuit including a first subcircuit, at least a second subcircuit, and power management circuitry. The power management circuitry is operable for estimating a metric indicative of a momentary supply voltage present at the first subcircuit based on a power supply current of the first subcircuit and a cross current flowing between the first subcircuit and the second subcircuit.