公开(公告)号：US09478655B2

公开(公告)日：2016-10-25

申请号：US14718443

申请日：2015-05-21

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/15 ,  H01L31/0312 ,  H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L29/167 ,  H01L21/04 ,  H01L29/423 ,  H01L29/04 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L29/7805 ,  H01L21/046 ,  H01L29/045 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/167 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/78 ,  H01L29/7804 ,  H01L29/7813 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes: a drift region, a source region, and a body region arranged between the source and drift regions; a diode region and a pn junction between the diode and drift regions; a trench having a first sidewall, a second sidewall opposite the first sidewall, and a bottom, the body region adjoining the first sidewall, the diode region adjoining the second sidewall, and the pn junction adjoining the bottom; a gate electrode in the trench and dielectrically insulated from the body, diode and drift regions by a gate dielectric. The diode region has a lower diode region arranged below the trench bottom, and the lower diode region has a maximum of a doping concentration distant to the trench bottom. A corresponding method of manufacturing the device also is provided.

Abstract translation: 半导体器件包括半导体本体和集成在半导体本体中的至少一个器件单元。 每个器件单元包括：漂移区，源区和布置在源极和漂移区之间的体区; 二极管区域和二极管与漂移区域之间的pn结; 具有第一侧壁，与第一侧壁相对的第二侧壁和底部，与第一侧壁邻接的主体区域，邻接第二侧壁的二极管区域和与底部相邻的pn结的沟槽; 沟槽中的栅极，并通过栅极电介质与体，二极管和漂移区介电绝缘。 二极管区域具有布置在沟槽底部下方的较低二极管区域，并且下二极管区域具有远离沟槽底部的掺杂浓度的最大值。 还提供了相应的制造装置的方法。

公开(公告)号：US20160172468A1

公开(公告)日：2016-06-16

申请号：US14567504

申请日：2014-12-11

Applicant: Infineon Technologies AG

Inventor： Romain Esteve ,  Dethard Peters ,  Wolfgang Bergner ,  Ralf Siemieniec ,  Thomas Aichinger ,  Daniel Kueck

IPC: H01L29/66 ,  H01L29/423 ,  H01L21/311 ,  H01L21/324 ,  H01L21/04 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L29/063 ,  H01L21/02236 ,  H01L21/045 ,  H01L21/0465 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L21/31111 ,  H01L21/324 ,  H01L21/3247 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: A silicon-carbide semiconductor substrate having a plurality of first doped regions being laterally spaced apart from one another and beneath a main surface, and a second doped region extending from the main surface to a third doped region that is above the first doped regions is formed. Fourth doped regions extending from the main surface to the first doped regions are formed. A gate trench having a bottom that is arranged over a portion of one of the first doped regions is formed. A high-temperature step is applied to the substrate so as to realign silicon-carbide atoms along sidewalls of the trench and form rounded corners in the gate trench. A surface layer that forms along the sidewalls of the gate trench during the high-temperature step from the substrate is removed.

Abstract translation: 一种碳化硅半导体衬底，其具有多个第一掺杂区域，该第一掺杂区域在主表面之间彼此横向间隔开，并且形成从主表面延伸至位于第一掺杂区域之上的第三掺杂区域的第二掺杂区域 。 形成从主表面延伸到第一掺杂区的第四掺杂区。 形成具有布置在一个第一掺杂区域的一部分上的底部的栅极沟槽。 将高温步骤施加到衬底上，以便沿着沟槽的侧壁重新排列碳化硅原子，并在栅极沟槽中形成圆角。 去除在离开衬底的高温步骤期间沿着栅极沟槽的侧壁形成的表面层。

公开(公告)号：US11764063B2

公开(公告)日：2023-09-19

申请号：US16886175

申请日：2020-05-28

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Romain Esteve ,  Moriz Jelinek ,  Caspar Leendertz ,  Werner Schustereder

IPC: H01L21/04 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/047 ,  H01L29/0634 ,  H01L29/1608 ,  H01L29/7813

Abstract: A silicon carbide substrate is provided that includes a drift layer of a first conductivity type and a trench extending from a main surface of the silicon carbide substrate into the drift layer. First dopants are implanted through a first trench sidewall of the trench. The first dopants have a second conductivity type and are implanted at a first implant angle into the silicon carbide substrate, wherein at the first implant angle channeling occurs in the silicon carbide substrate. The first dopants form a first compensation layer extending parallel to the first trench sidewall.

公开(公告)号：US11101343B2

公开(公告)日：2021-08-24

申请号：US16404284

申请日：2019-05-06

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Thomas Basler ,  Wolfgang Bergner ,  Rudolf Elpelt ,  Romain Esteve ,  Michael Hell ,  Daniel Kueck ,  Caspar Leendertz ,  Dethard Peters ,  Hans-Joachim Schulze

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10

Abstract: A semiconductor component has a gate structure that extends from a first surface into an SiC semiconductor body. A body area in the SiC semiconductor body adjoins a first side wall of the gate structure. A first shielding area and a second shielding area of the conductivity type of the body area have at least twice as high a level of doping as the body area. A diode area forms a Schottky contact with a load electrode between the first shielding area and the second shielding area.

公开(公告)号：US20210167203A1

公开(公告)日：2021-06-03

申请号：US17172680

申请日：2021-02-10

Applicant: Infineon Technologies AG

Inventor： Andreas Peter Meiser ,  Romain Esteve ,  Roland Rupp

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L29/739 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/423

Abstract: A method of manufacturing semiconductor devices includes: forming source regions of a first conductivity type in a SiC-based semiconductor substrate, wherein dopants are introduced selectively through first segments of first mask openings in a first dopant mask and wherein a longitudinal axis of the first mask opening extends into a first horizontal direction; forming pinning regions of a complementary second conductivity type, wherein dopants are selectively introduced through second segments of the first mask openings and wherein the first and second segments alternate along the first horizontal direction; and forming body regions of the second conductivity type, wherein dopants are selectively introduced through second mask openings in a second dopant mask, wherein a width of the second mask openings along a second horizontal direction orthogonal to the first horizontal direction is greater than a width of the first mask openings.

公开(公告)号：US20210013310A1

公开(公告)日：2021-01-14

申请号：US16926695

申请日：2020-07-11

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Romain Esteve ,  Moriz Jelinek ,  Anton Mauder ,  Hans-Joachim Schulze ,  Werner Schustereder

IPC: H01L29/16 ,  H01L29/06

Abstract: First dopants are implanted through a larger opening of a first process mask into a silicon carbide body, wherein the larger opening exposes a first surface section of the silicon carbide body. A trench is formed in the silicon carbide body in a second surface section exposed by a smaller opening in a second process mask. The second surface section is a sub-section of the first surface section. The larger opening and the smaller opening are formed self-aligned to each other. At least part of the implanted first dopants form at least one compensation layer portion extending parallel to a trench sidewall.

公开(公告)号：US10734514B2

公开(公告)日：2020-08-04

申请号：US16054419

申请日：2018-08-03

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Romain Esteve ,  Dethard Peters ,  Roland Rupp ,  Ralf Siemieniec

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/739 ,  H01L27/06 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/36 ,  H01L29/861 ,  H01L29/872 ,  H01L29/04

Abstract: A semiconductor device includes trench structures that extend from a first surface into a semiconductor body. The trench structures include a gate structure and a contact structure that extends through the gate structure, respectively. Transistor mesas are between the trench structures. Each transistor mesa includes a body zone forming a first pn junction with a drift structure and a second pn junction with a source zone. Diode regions directly adjoin one of the contact structures form a third pn junction with the drift structure, respectively.

公开(公告)号：US10700192B2

公开(公告)日：2020-06-30

申请号：US16256453

申请日：2019-01-24

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Wolfgang Bergner ,  Romain Esteve ,  Dethard Peters

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L29/06 ,  H01L29/872 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/36 ,  H01L29/861

Abstract: A semiconductor device includes a semiconductor body and at least one device cell integrated in the semiconductor body. Each device cell includes a drift region, a source region, and a body region arranged between the source region and the drift region. A gate trench extends from a first surface of the semiconductor body, through the source and body regions and into the drift region. A diode region extends under the gate trench. A pn junction is formed between the diode and drift regions below the gate trench. A gate electrode arranged in the gate trench is dielectrically insulated from the source, body, diode and drift regions by a gate dielectric. A contact trench spaced apart from the gate trench extends from the first surface into the source region. A source electrode arranged in the contact trench adjoins the source region at a sidewall of the contact trench.

公开(公告)号：US20190311966A1

公开(公告)日：2019-10-10

申请号：US16379289

申请日：2019-04-09

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L23/532 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L21/56

Abstract: A semiconductor device includes a contact metallization layer arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, and an organic passivation layer. The organic passivation layer is located between the contact metallization layer and the inorganic passivation structure, and located vertically closer to the semiconductor substrate than a part of the organic passivation layer located on top of the inorganic passivation structure.

公开(公告)号：US10217636B2

公开(公告)日：2019-02-26

申请号：US15919918

申请日：2018-03-13

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Victorina Poenariu ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Gerald Reinwald ,  Roland Rupp ,  Gerald Unegg

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/10 ,  H01L29/78 ,  H01L29/40 ,  H01L29/861 ,  H01L29/06 ,  H01L21/3065 ,  H01L29/423

Abstract: A trench is formed that extends from a main surface into a crystalline silicon carbide semiconductor layer. A mask is formed that includes a mask opening exposing the trench and a rim section of the main surface around the trench. By irradiation with a particle beam a first portion of the semiconductor layer exposed by the mask opening and a second portion outside of the vertical projection of the mask opening and directly adjoining to the first portion are amorphized. A vertical extension of the amorphized second portion gradually decreases with increasing distance to the first portion. The amorphized first and second portions are removed.