公开(公告)号：US10475743B2

公开(公告)日：2019-11-12

申请号：US15458366

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Mueller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.

公开(公告)号：US20170345711A1

公开(公告)日：2017-11-30

申请号：US15602451

申请日：2017-05-23

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Frank Umbach

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L21/76825 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/02145 ,  H01L2224/04042 ,  H01L2224/05096 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2924/3512 ,  H01L2924/00014 ,  H01L2924/01025 ,  H01L2924/01201 ,  H01L2924/20755 ,  H01L2924/2076

Abstract: A method for forming a semiconductor device includes forming an insulating material layer above a semiconductor substrate and modifying at least a portion of a surface of the insulating material layer after forming the insulating material layer. Further, the method includes forming an electrical conductive structure on at least the portion of the surface of the insulating material layer after modifying at least the portion of the surface of the insulating material layer.

公开(公告)号：US20170098620A1

公开(公告)日：2017-04-06

申请号：US15285250

申请日：2016-10-04

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Wolfgang Wagner

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05118 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/4502 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014

Abstract: A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

公开(公告)号：US20160218033A1

公开(公告)日：2016-07-28

申请号：US14607708

申请日：2015-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ravi Keshav Joshi ,  Juergen Steinbrenner ,  Christian Fachmann ,  Petra Fischer ,  Roman Roth

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

Abstract translation: 在半导体衬底上形成金属化层的方法包括在层间电介质层上沉积扩散阻挡衬垫的覆盖层，以及在扩散阻挡衬里上沉积中间层的覆盖层。 包含铜的功率金属层的覆盖层沉积在中间层上。 中间层包括多数元素和铜的固溶体。 中间层具有与功率金属层不同的蚀刻选择性。 在沉积功率金属层之后，构建功率金属层，中间层和扩散阻挡衬里。