公开(公告)号：US20200013722A1

公开(公告)日：2020-01-09

申请号：US16577316

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Müller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

公开(公告)号：US20160049463A1

公开(公告)日：2016-02-18

申请号：US14457491

申请日：2014-08-12

Applicant: Infineon Technologies AG

Inventor： Karin Buchholz ,  Matteo Dainese ,  Elmar Falck ,  Hans-Joachim Schulze ,  Gerhard Schmidt ,  Frank Umbach

IPC: H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A semiconductor device has a semiconductor body including opposing bottom and top sides, a surface surrounding the semiconductor body, an active semiconductor region formed in the semiconductor body, an edge region surrounding the active semiconductor region, a first semiconductor zone of a first conduction type formed in the edge region, an edge termination structure formed in the edge region at the top side, and a shielding structure arranged on that side of the edge termination structure facing away from the bottom side. The shielding structure has a number of N1≧2 first segments and a number of N2≧1 second segments. Each of the first segments is electrically connected to each of the other first segments and to each of the second segments, and each of the second segments has an electric resistivity higher than an electric resistivity of each of the first segments.

Abstract translation: 半导体器件具有半导体本体，该半导体本体包括相对的底部和顶侧，围绕半导体本体的表面，形成在半导体本体中的有源半导体区域，围绕有源半导体区域的边缘区域，形成第一导电类型的第一半导体区域 在边缘区域中，形成在顶侧的边缘区域中的边缘终端结构以及布置在边缘终端结构的背离底侧的那一侧的屏蔽结构。 屏蔽结构具有多个N1≥2个第一段和N 2个≥1个第二段。 每个第一段电连接到每个其它第一段和每个第二段，并且每个第二段具有高于每个第一段的电阻率的电阻率。

公开(公告)号：US09741639B2

公开(公告)日：2017-08-22

申请号：US14027603

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Frank Umbach ,  Niels Oeschler ,  Kirill Trunov

IPC: H01L23/48 ,  H01L21/336 ,  H01L21/50 ,  H01L23/00

CPC classification number: H01L23/48 ,  H01L21/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/2908 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1≧1 or N1≧2 of first partial layers and a number N2≧2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.

公开(公告)号：US10777506B2

公开(公告)日：2020-09-15

申请号：US16577316

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Müller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

公开(公告)号：US10224237B2

公开(公告)日：2019-03-05

申请号：US15602451

申请日：2017-05-23

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Frank Umbach

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: A method for forming a semiconductor device includes forming an insulating material layer above a semiconductor substrate and modifying at least a portion of a surface of the insulating material layer after forming the insulating material layer. Further, the method includes forming an electrical conductive structure on at least the portion of the surface of the insulating material layer after modifying at least the portion of the surface of the insulating material layer.

公开(公告)号：US09281360B1

公开(公告)日：2016-03-08

申请号：US14457491

申请日：2014-08-12

Applicant: Infineon Technologies AG

Inventor： Karin Buchholz ,  Matteo Dainese ,  Elmar Falck ,  Hans-Joachim Schulze ,  Gerhard Schmidt ,  Frank Umbach

IPC: H01L29/02 ,  H01L29/06 ,  H01L29/40

CPC classification number: H01L29/0615 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/0638 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611 ,  H01L29/872

Abstract: A semiconductor device has a semiconductor body including opposing bottom and top sides, a surface surrounding the semiconductor body, an active semiconductor region formed in the semiconductor body, an edge region surrounding the active semiconductor region, a first semiconductor zone of a first conduction type formed in the edge region, an edge termination structure formed in the edge region at the top side, and a shielding structure arranged on that side of the edge termination structure facing away from the bottom side. The shielding structure has a number of N1≧2 first segments and a number of N2≧1 second segments. Each of the first segments is electrically connected to each of the other first segments and to each of the second segments, and each of the second segments has an electric resistivity higher than an electric resistivity of each of the first segments.

Abstract translation: 半导体器件具有半导体本体，该半导体本体包括相对的底部和顶侧，围绕半导体主体的表面，形成在半导体本体中的有源半导体区域，围绕有源半导体区域的边缘区域，形成第一导电类型的第一半导体区域 在边缘区域中，形成在顶侧的边缘区域中的边缘终端结构以及布置在边缘终端结构的背离底侧的那一侧的屏蔽结构。 屏蔽结构具有多个N1≥2个第一段和N 2个≥1个第二段。 每个第一段电连接到每个其它第一段和每个第二段，并且每个第二段具有高于每个第一段的电阻率的电阻率。

公开(公告)号：US20150303260A1

公开(公告)日：2015-10-22

申请号：US14679514

申请日：2015-04-06

Applicant: Infineon Technologies AG

Inventor： Franz Josef Niedernostheide ,  Manfred Pfaffenlehner ,  Hans-Joachim Schulze ,  Holger Schulze ,  Frank Umbach ,  Christoph Weiss

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/861 ,  H01L21/283 ,  H01L29/66 ,  H01L23/31 ,  H01L21/56 ,  H01L29/739 ,  H01L29/40

CPC classification number: H01L29/0696 ,  H01L23/3157 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66128 ,  H01L29/66333 ,  H01L29/6634 ,  H01L29/66712 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7811 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor body includes first and second opposing surfaces, an edge extending in a vertical direction substantially perpendicular to the first surface, an active area, a peripheral area arranged in a horizontal direction substantially parallel to the first surface between the active area and edge, and a pn-junction extending from the active area into the peripheral area. In the peripheral area the semiconductor device further includes a first conductive region arranged next to the first surface, a second conductive region arranged next to the first surface, and arranged in the horizontal direction between the first conductive region and edge, and a passivation structure including a first portion at least partly covering the first conductive region, a second portion at least partly covering the second conductive region. The first portion has a different layer composition than the second portion and/or a thickness which differs from the thickness of the second portion.

Abstract translation: 半导体本体包括第一和第二相对表面，沿基本上垂直于第一表面的垂直方向延伸的边缘，有效区域，沿着基本上平行于有效区域和边缘之间的第一表面的水平方向布置的外围区域，以及 从有源区延伸到周边区域的pn结。 在外围区域中，半导体器件还包括邻近第一表面布置的第一导电区域，邻近第一表面设置并沿第一导电区域和边缘之间的水平方向布置的第二导电区域，以及包括 至少部分地覆盖所述第一导电区域的第一部分，至少部分地覆盖所述第二导电区域的第二部分。 第一部分具有不同于第二部分的层组成和/或与第二部分的厚度不同的厚度。

公开(公告)号：US20140077376A1

公开(公告)日：2014-03-20

申请号：US14027603

申请日：2013-09-16

Applicant: Infineon Technologies AG

Inventor： Frank Umbach ,  Niels Oeschler ,  Kirill Trunov

IPC: H01L23/48 ,  H01L21/50

CPC classification number: H01L23/48 ,  H01L21/50 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/2908 ,  H01L2224/29111 ,  H01L2224/29116 ,  H01L2224/29118 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83385 ,  H01L2224/8381 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01079

Abstract: A semiconductor chip includes a semiconductor body and a chip metallization applied on the semiconductor body. The chip metallization has an underside facing away from the semiconductor body. The chip further includes a layer stack applied to the underside of the chip metallization and having a number N1≧1 or N1≧2 of first partial layers and a number N2≧2 of second partial layers. The first partial layers and the second partial layers are arranged alternately and successively such that at least one of the second partial layers is arranged between the first partial layers of each first pair of the first partial layers and such that at least one of the first partial layers is arranged between the second partial layers of each second pair of the second partial layers.

Abstract translation: 半导体芯片包括半导体本体和施加在半导体本体上的芯片金属化。 芯片金属化具有背向半导体本体的底面。 芯片还包括施加到芯片金属化的下侧的层叠体，并且具有第一部分层的数量N1≥1或N1≥2以及第二部分层的数量N2≥2。 第一部分层和第二部分层被交替且相继地布置，使得第二部分层中的至少一个布置在每个第一对第一部分层的第一部分层之间，并且使得第一部分层和第二部分层中的至少一个 每层第二部分层的第二部分层之间布置有层。

公开(公告)号：US20230048908A1

公开(公告)日：2023-02-16

申请号：US17881740

申请日：2022-08-05

Applicant: Infineon Technologies AG

Inventor： Damiano Cassese ,  Andreas Korzenietz ,  Holger Schulze ,  Frank Umbach

IPC: H01L29/40 ,  H01L29/06

Abstract: A method of producing a power semiconductor device includes: providing a semiconductor body; forming, at the semiconductor body, a polycrystalline semiconductor region; forming, at the polycrystalline semiconductor region, an amorphous sublayer; subjecting the amorphous sublayer to a re-crystallization processing step to form a re-crystallized sublayer; and forming a metal layer at the re-crystallized sublayer.

公开(公告)号：US10957764B2

公开(公告)日：2021-03-23

申请号：US14679514

申请日：2015-04-06

Applicant: Infineon Technologies AG

Inventor： Franz Josef Niedernostheide ,  Manfred Pfaffenlehner ,  Hans-Joachim Schulze ,  Holger Schulze ,  Frank Umbach ,  Christoph Weiss

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/40 ,  H01L29/861 ,  H01L23/31 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

Abstract: A semiconductor body includes first and second opposing surfaces, an edge extending in a vertical direction substantially perpendicular to the first surface, an active area, a peripheral area arranged in a horizontal direction substantially parallel to the first surface between the active area and edge, and a pn-junction extending from the active area into the peripheral area. In the peripheral area the semiconductor device further includes a first conductive region arranged next to the first surface, a second conductive region arranged next to the first surface, and arranged in the horizontal direction between the first conductive region and edge, and a passivation structure including a first portion at least partly covering the first conductive region, a second portion at least partly covering the second conductive region. The first portion has a different layer composition than the second portion and/or a thickness which differs from the thickness of the second portion.