公开(公告)号：US20190089064A1

公开(公告)日：2019-03-21

申请号：US16050112

申请日：2018-07-31

Applicant: Integrated Device Technology, Inc.

Inventor： Samet Zihir ,  Tumay Kanar

IPC: H01Q21/00 ,  H01Q21/06 ,  H01Q19/30 ,  H01Q3/36 ,  H01Q3/28 ,  H01Q1/52

Abstract: An apparatus includes a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. Each antenna element may include a dual-pole antenna having a vertical feed and a horizontal feed. The beam former circuit may be (i) disposed in the package, (ii) have a plurality of pairs of ports, (iii) configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) configured to receive the radio-frequency signals at the ports while in a receive mode. Each pair of the ports is configured to be directly connected to a respective one of the antenna elements. All of the ports may be spatially routed into alignment with the vertical feeds and the horizontal feeds in a single conductive plane of the antenna array.

公开(公告)号：US11171427B2

公开(公告)日：2021-11-09

申请号：US16747054

申请日：2020-01-20

Applicant: Integrated Device Technology, Inc.

Inventor： Samet Zihir ,  Tumay Kanar

IPC: H01Q21/00 ,  H01Q21/06 ,  H04B1/44 ,  H03F1/56 ,  H03F3/19 ,  H03G3/30 ,  H03F3/24 ,  H03F1/32 ,  H03F3/195 ,  H03F3/45 ,  H03F3/68 ,  H04B1/04 ,  H04B1/18 ,  H04B1/48 ,  H03K21/10 ,  H04B7/06 ,  H01Q1/52 ,  H01Q3/28 ,  H01Q3/36 ,  H01Q19/30 ,  H03F1/02 ,  H01Q1/48 ,  H01Q1/22 ,  H03H7/48 ,  H04B1/401

Abstract: An apparatus includes a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. Each antenna element may include a dual-pole antenna having a vertical feed and a horizontal feed. The beam former circuit may be (i) disposed in the package, (ii) have a plurality of pairs of ports, (iii) configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) configured to receive the radio-frequency signals at the ports while in a receive mode. Each pair of the ports is configured to be directly connected to a respective one of the antenna elements. All of the ports may be spatially routed into alignment with the vertical feeds and the horizontal feeds in a single conductive plane of the antenna array.

公开(公告)号：US20210151878A1

公开(公告)日：2021-05-20

申请号：US16683472

申请日：2019-11-14

Applicant: Integrated Device Technology, Inc.

Inventor： Morteza Abbasi ,  Tumay Kanar ,  Naveen Krishna Yanduru

IPC: H01Q3/26 ,  H01Q3/38 ,  H04B1/40

Abstract: An apparatus includes a plurality of transceiver circuits, each comprising one or more phase shifter circuits. The phase shifter circuits may be configured to make a phase change by switching at least one of a capacitance value and an inductance value in response to a control signal. A characteristic impedance and the phase of each phase shifter circuit are correlated such that after the phase change, a value of the characteristic impedance is maintained at a predefined value.

公开(公告)号：US10790594B2

公开(公告)日：2020-09-29

申请号：US16131296

申请日：2018-09-14

Applicant: Integrated Device Technology, Inc.

Inventor： Tumay Kanar ,  Samet Zihir ,  Naveen Krishna Yanduru

IPC: H03F3/45 ,  H01Q21/00 ,  H04B1/44 ,  H03F1/56 ,  H03F3/19 ,  H03G3/30 ,  H03F3/24 ,  H03F1/32 ,  H03F3/195 ,  H03F3/68 ,  H04B1/04 ,  H04B1/18 ,  H04B1/48 ,  H03K21/10 ,  H04B7/06 ,  H01Q1/52 ,  H01Q3/28 ,  H01Q3/36 ,  H01Q19/30 ,  H01Q21/06 ,  H03F1/02 ,  H01Q1/48 ,  H01Q1/22 ,  H03H7/48 ,  H04B1/401

Abstract: An apparatus includes a first circuit and a plurality of second circuits. The first circuit may be configured to generate a pair of quadrature signals from a radio-frequency signal. The second circuits may each comprise a plurality of cascode amplifiers. The cascode amplifiers may be connected in parallel. The cascode amplifiers may be configured to generate a plurality of intermediate signals by modulating the quadrature signals in response to a first control signal and a second control signal. The first control signal generally switches a contribution of the cascode amplifiers in the generation of the intermediate signal. The second control signal may adjusts a total current passing through all of the cascode amplifiers.

公开(公告)号：US10763913B1

公开(公告)日：2020-09-01

申请号：US16372698

申请日：2019-04-02

Applicant: Integrated Device Technology, Inc.

Inventor： Himanshu Khatri ,  Samet Zihir ,  Tumay Kanar

IPC: H04B1/44 ,  H04B1/18 ,  H03F3/19 ,  H03G3/30 ,  H03F3/04 ,  H04B1/04

Abstract: An apparatus includes a log amplifier and a calibration circuit. The log amplifier may be configured to generate an output signal in response to an offset between a first voltage and a second voltage. The calibration circuit may be configured to disconnect an input power and perform a cancellation of the offset when the input power is not present. The first voltage may be generated by the apparatus in response to a power detection. The second voltage may be received from a reference circuit. The cancellation of the offset may extend a working range of the apparatus. The output may provide a linear-in-dB power detection.

公开(公告)号：US10587052B2

公开(公告)日：2020-03-10

申请号：US16050112

申请日：2018-07-31

Applicant: Integrated Device Technology, Inc.

Inventor： Samet Zihir ,  Tumay Kanar

IPC: H01Q21/00 ,  H01Q21/06 ,  H04B1/44 ,  H03F1/56 ,  H03F3/19 ,  H03G3/30 ,  H03F3/24 ,  H03F1/32 ,  H03F3/195 ,  H03F3/45 ,  H03F3/68 ,  H04B1/04 ,  H04B1/18 ,  H04B1/48 ,  H03K21/10 ,  H04B7/06 ,  H01Q1/52 ,  H01Q3/28 ,  H01Q3/36 ,  H01Q19/30 ,  H03F1/02 ,  H01Q1/48 ,  H01Q1/22 ,  H03H7/48 ,  H04B1/401

Abstract: An apparatus includes a package and a beam former circuit. The package may be configured to be mounted on an antenna array at a center of four antenna elements. Each antenna element may include a dual-pole antenna having a vertical feed and a horizontal feed. The beam former circuit may be (i) disposed in the package, (ii) have a plurality of pairs of ports, (iii) configured to generate a plurality of radio-frequency signals in the ports while in a transmit mode and (iv) configured to receive the radio-frequency signals at the ports while in a receive mode. Each pair of the ports is configured to be directly connected to a respective one of the antenna elements. All of the ports may be spatially routed into alignment with the vertical feeds and the horizontal feeds in a single conductive plane of the antenna array.

公开(公告)号：US20190221947A1

公开(公告)日：2019-07-18

申请号：US16267627

申请日：2019-02-05

Applicant: Integrated Device Technology, Inc.

Inventor： Samet Zihir ,  Tumay Kanar

IPC: H01Q21/24 ,  H01Q3/28 ,  H04B7/10 ,  H04B7/06

CPC classification number: H01Q21/245 ,  H01Q3/28 ,  H04B7/0617 ,  H04B7/10

Abstract: An apparatus includes a phased array antenna panel and one or more dual-polarization beam former circuits mounted on the phased array antenna panel. The phased array antenna panel generally comprises a plurality of dual-polarization antenna elements. The plurality of dual-polarization antenna elements are generally arranged in one or more groups. Each dual-polarization beam former circuit may be coupled to a respective group of the dual-polarization antenna elements. Each dual-polarization beam former circuit generally comprises a plurality of transceiver channels. Each transceiver channel generally comprises a horizontal channel and a vertical channel. Each dual-polarization beam former circuit provides polarization rotation through bias current control in each of the vertical and horizontal channels.

公开(公告)号：US20190089400A1

公开(公告)日：2019-03-21

申请号：US16105207

申请日：2018-08-20

Applicant: Integrated Device Technology, Inc.

Inventor： Samet Zihir ,  Naveen Krishna Yanduru ,  Tumay Kanar

IPC: H04B1/44 ,  H03F3/24 ,  H03G3/30 ,  H04B7/06 ,  H03F3/19 ,  H03F1/56 ,  H03K21/10

CPC classification number: H01Q21/0006 ,  H01Q1/2283 ,  H01Q1/48 ,  H01Q1/523 ,  H01Q1/526 ,  H01Q3/28 ,  H01Q3/36 ,  H01Q19/30 ,  H01Q21/0025 ,  H01Q21/062 ,  H01Q21/065 ,  H03F1/0211 ,  H03F1/0261 ,  H03F1/3282 ,  H03F1/565 ,  H03F3/19 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45089 ,  H03F3/45475 ,  H03F3/68 ,  H03F2200/294 ,  H03F2200/387 ,  H03F2200/451 ,  H03G3/3042 ,  H03H7/487 ,  H03K21/10 ,  H04B1/0458 ,  H04B1/18 ,  H04B1/401 ,  H04B1/44 ,  H04B1/48 ,  H04B7/0617

Abstract: An apparatus includes an impedance matching network, a first switch circuit, and a second switch circuit. The impedance matching network generally comprises a first port, a second port, and a third port. The first switch circuit may be coupled between the first port and a circuit ground potential. The second switch circuit may be coupled between the second port and the circuit ground potential. The impedance matching network generally provides a first impedance value for the first port and for the third port when the second port is connected to the circuit ground potential. The impedance matching network generally provides a second impedance value for the second port and for the third port when the first port is connected to the circuit ground potential. The first impedance value and the second impedance value are asymmetrical.

公开(公告)号：US20190089308A1

公开(公告)日：2019-03-21

申请号：US16131296

申请日：2018-09-14

Applicant: Integrated Device Technology, Inc.

Inventor： Tumay Kanar ,  Samet Zihir ,  Naveen Krishna Yanduru

IPC: H03F1/02 ,  H03F3/19

Abstract: An apparatus includes a first circuit and a plurality of second circuits. The first circuit may be configured to generate a pair of quadrature signals from a radio-frequency signal. The second circuits may each comprise a plurality of cascode amplifiers. The cascode amplifiers may be connected in parallel. The cascode amplifiers may be configured to generate a plurality of intermediate signals by modulating the quadrature signals in response to a first control signal and a second control signal. The first control signal generally switches a contribution of the cascode amplifiers in the generation of the intermediate signal. The second control signal may adjusts a total current passing through all of the cascode amplifiers.

公开(公告)号：US20200244228A1

公开(公告)日：2020-07-30

申请号：US16258145

申请日：2019-01-25

Applicant: Integrated Device Technology, Inc.

Inventor： Samet Zihir ,  Himanshu Khatri ,  Tumay Kanar

IPC: H03F1/08 ,  H03F1/02 ,  H03F3/24

Abstract: An apparatus comprises an amplifier circuit and a bias circuit. The bias circuit is generally configured to dynamically adjust a bias voltage reference at a bias node connected to one or more input transistors of the amplifier circuit to maintain a low baseband impedance.