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公开(公告)号：US10290289B2
公开(公告)日：2019-05-14
申请号：US15477047
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Sanjeev S. Jahagirdar , Tapan A. Ganpule , Anupama A. Thaploo , Abishek R. Appu , Joydeep Ray , Altug Koker
Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.
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公开(公告)号：US10062429B1
公开(公告)日：2018-08-28
申请号：US15488681
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Bhushan Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhisek R. Appu
IPC: G11C5/05 , G11C11/4094 , G06F3/06 , G11C11/4074 , G11C11/4093 , G06F13/40 , G06F9/38
CPC classification number: G11C11/4094 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G06F9/3867 , G06F9/3887 , G06F12/08 , G06F12/0868 , G06F12/0897 , G06F12/1027 , G06F12/109 , G06F13/4068 , G11C11/4074 , G11C11/4093 , G11C11/419 , Y02D10/14 , Y02D10/151
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US11176990B2
公开(公告)日：2021-11-16
申请号：US17018071
申请日：2020-09-11
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhishek R. Appu
IPC: G11C7/00 , G11C11/4094 , G06F9/30 , G06F12/0868 , G06F12/1027 , G11C11/4074 , G11C11/4093 , G06F13/40 , G06F9/38 , G11C11/419 , G06F12/0897 , G06F12/109 , G06F3/06 , G06F12/08
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US10817012B2
公开(公告)日：2020-10-27
申请号：US16527165
申请日：2019-07-31
Applicant: Intel Corporation
Inventor： Iqbal R. Rajwani , Altug Koker , Bhushan M. Borole , Kamal Sinha , Abhishek R. Appu , Anupama A. Thaploo , Sunil Nekkanti , Wenyin Fu
IPC: G06F1/06 , G06F1/08 , H03K19/09 , G06F9/38 , G06F13/16 , H03K19/096 , G06T1/60 , G06F9/30 , G06F1/14
Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.
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公开(公告)号：US10587244B2
公开(公告)日：2020-03-10
申请号：US16180604
申请日：2018-11-05
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Anupama A. Thaploo , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.
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Patent Agency Ranking
公开(公告)号：US10418076B2
公开(公告)日：2019-09-17
申请号：US15706521
申请日：2017-09-15
Applicant: Intel Corporation
Inventor： Pascal A. Meinerzhagen , Stephen T. Kim , Anupama A. Thaploo , Muhammad M. Khellah
IPC: G11C5/14
Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.
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公开(公告)号：US20190035452A1
公开(公告)日：2019-01-31
申请号：US16054207
申请日：2018-08-03
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Iqbal R. Rajwani , Anupama A. Thaploo , Sunil Nekkanti , Altug Koker , Abhisek R. Appu
IPC: G11C11/4094 , G06F3/06 , G11C11/4093 , G06F13/40 , G06F9/38 , G11C11/4074
CPC classification number: G11C11/4094 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G06F9/3867 , G06F9/3887 , G06F12/0868 , G06F12/0897 , G06F12/1027 , G06F12/109 , G06F13/4068 , G11C11/4074 , G11C11/4093 , G11C11/419 , Y02D10/14 , Y02D10/151
Abstract: In one embodiment, a graphics processor includes a register file having a plurality of storage segments to store information and output a plurality of segment outputs via a plurality of segmented bitlines to a static logic circuit to receive the plurality of segment outputs from the plurality of storage segments and to output read data based on the plurality of segment outputs. The register file may output the read data with a same amount of power without regard to a logic state of the read data. Other embodiments are described and claimed.
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公开(公告)号：US10158346B2
公开(公告)日：2018-12-18
申请号：US15488628
申请日：2017-04-17
Applicant: Intel Corporation
Inventor： Bhushan M. Borole , Anupama A. Thaploo , Altug Koker , Abhishek R. Appu , Kamal Sinha , Wenyin Fu
Abstract: A pulse triggered flip flop circuit includes an exclusive OR clock generating stage that receives an input clock, data and produces an output clock pulse. The stage produces a output clock pulse that only goes away when the data is fully captured. The stage disables the output clock pulse only when the data is fully captured. Moreover, the circuit only toggles when the input data changes, reducing power consumption in some embodiments.
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公开(公告)号：US20180286360A1
公开(公告)日：2018-10-04
申请号：US15477047
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Sanjeev S. Jahagirdar , Tapan A. Ganpule , Anupama A. Thaploo , Abhishek R. Appu , Joydeep Ray , Altug Koker
CPC classification number: G09G5/393 , G06F13/4072 , G06F13/4086 , G09G5/022 , G09G5/346 , G09G5/37 , G09G5/399 , H03K19/0002 , H03K19/0813 , Y02D10/14 , Y02D10/151
Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.
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公开(公告)号：US11081091B2
公开(公告)日：2021-08-03
申请号：US16658793
申请日：2019-10-21
Applicant: Intel Corporation
Inventor： Sanjeev S. Jahagirdar , Tapan A. Ganpule , Anupama A. Thaploo , Abhishek R. Appu , Joydeep Ray , Altug Koker
IPC: G09G5/393 , G09G5/399 , G06F13/40 , G09G5/02 , G09G5/37 , G09G5/34 , H03K19/00 , H03K19/08 , G06F3/14 , G09G5/36
Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.
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