公开(公告)号：US10290289B2

公开(公告)日：2019-05-14

申请号：US15477047

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Sanjeev S. Jahagirdar ,  Tapan A. Ganpule ,  Anupama A. Thaploo ,  Abishek R. Appu ,  Joydeep Ray ,  Altug Koker

IPC: G09G5/393 ,  G09G5/399 ,  G06F13/40 ,  G09G5/02 ,  G09G5/37 ,  G09G5/34 ,  H03K19/00 ,  H03K19/08

Abstract: Methods and apparatus relating to an adaptive multibit bus for energy optimization are described. In an embodiment, a 1-bit interconnect of a processor is caused to select between a plurality of operational modes. The plurality of operational modes comprises a first mode and a second mode. The first mode causes transmission of a single bit over the 1-bit interconnect at a first frequency and the second mode causes transmission of a plurality of bits over the 1-bit interconnect at a second frequency based at least in part on a determination that an operating voltage of the 1-bit interconnect is at a high voltage level and that the second frequency is lower than the first frequency. Other embodiments are also disclosed and claimed.