公开(公告)号：US20220199628A1

公开(公告)日：2022-06-23

申请号：US17129869

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Noriyuki SATO ,  Sarah ATANASOV ,  Abhishek A. SHARMA ,  Bernhard SELL ,  Chieh-Jen KU ,  Arnab SEN GUPTA ,  Matthew V. METZ ,  Elliot N. TAN ,  Hui Jae YOO ,  Travis W. LAJOIE ,  Van H. LE ,  Pei-Hua WANG

IPC: H01L27/108 ,  H01L29/786

Abstract: An integrated circuit (IC) structure in a memory device is described. In an example, the IC structure includes a memory cell including a bitline (BL) extending along a first direction and a channel extending along a second direction above and diagonal to the BL. In the example, a wordline (WL) extends in a third direction perpendicular to the first direction of the BL and intersects with the channel to control a current in the channel along a gated channel length. In some examples, the channel is electrically coupled on a first side to a storage capacitor via a storage node contact (SNC) and on a second side to the BL via a bit line contact (BLC) located on an underside or backside of the channel.

公开(公告)号：US20220005953A1

公开(公告)日：2022-01-06

申请号：US17475196

申请日：2021-09-14

Applicant: Intel Corporation

Inventor： Bernhard SELL

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L27/092 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US20190304897A1

公开(公告)日：2019-10-03

申请号：US15943565

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Travis LAJOIE ,  Abhishek SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532 ,  H01L27/108

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.

公开(公告)号：US20220310849A1

公开(公告)日：2022-09-29

申请号：US17840186

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Juan ALZATE VINASCO

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/108 ,  H01L29/49

Abstract: Embodiments herein describe techniques for a semiconductor device including a capacitor and a transistor above the capacitor. A contact electrode may be shared between the capacitor and the transistor. The capacitor includes a first plate above a substrate, and the shared contact electrode above the first plate and separated from the first plate by a capacitor dielectric layer, where the shared contact electrode acts as a second plate for the capacitor. The transistor includes a gate electrode above the substrate and above the capacitor; a channel layer separated from the gate electrode by a gate dielectric layer, and in contact with the shared contact electrode; and a source electrode above the channel layer, separated from the gate electrode by the gate dielectric layer, and in contact with the channel layer. The shared contact electrode acts as a drain electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US20220246529A1

公开(公告)日：2022-08-04

申请号：US17723309

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Bernhard SELL ,  Oleg GOLONZKA

IPC: H01L23/535 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20200350412A1

公开(公告)日：2020-11-05

申请号：US16400758

申请日：2019-05-01

Applicant: Intel Corporation

Inventor： Chieh-Jen KU ,  Bernhard SELL ,  Pei-Hua WANG ,  Gregory GEORGE ,  Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Juan G. ALZATE VINASCO

IPC: H01L29/22 ,  H01L29/66 ,  H01L29/786

Abstract: Thin film transistors having alloying source or drain metals are described. In an example, an integrated circuit structure includes a semiconducting oxide material over a gate electrode. A pair of conductive contacts is on a first region of the semiconducting oxide material. A second region of the semiconducting oxide material is between the pair of conductive contacts. The pair of conductive contacts includes a metal species. The metal species is in the first region of the semiconducting oxide material but not in the second region of the semiconducting oxide material.

公开(公告)号：US20200243517A1

公开(公告)日：2020-07-30

申请号：US16257855

申请日：2019-01-25

Applicant: Intel Corporation

Inventor： Guannan LIU ,  Akm A. AHSAN ,  Mark ARMSTRONG ,  Bernhard SELL

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

公开(公告)号：US20200235241A1

公开(公告)日：2020-07-23

申请号：US16838359

申请日：2020-04-02

Applicant: Intel Corporation

Inventor： Bernhard SELL

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L29/165 ,  H01L29/10 ,  H01L29/08 ,  H01L29/16 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L29/06 ,  H01L27/092 ,  H01L27/12 ,  H01L29/417 ,  H01L27/108 ,  H01L27/088 ,  H01L29/786

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US20250029926A1

公开(公告)日：2025-01-23

申请号：US18909539

申请日：2024-10-08

Applicant: Intel Corporation

Inventor： Bernhard SELL ,  Oleg GOLONZKA

IPC: H01L23/535 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088 ,  H01L29/08 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20240222509A1

公开(公告)日：2024-07-04

申请号：US18608294

申请日：2024-03-18

Applicant: Intel Corporation

Inventor： Bernhard SELL

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16 ,  H01L29/165 ,  H01L29/417 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L29/7853 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3083 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H01L29/7856 ,  H01L29/786 ,  H10B12/056 ,  H10B12/36 ,  H01L2924/13067

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.