公开(公告)号：US20210305255A1

公开(公告)日：2021-09-30

申请号：US16828507

申请日：2020-03-24

Applicant: Intel Corporation

Inventor： Juan G. ALZATE VINASCO ,  Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Kimberly L. PIERCE ,  Elliot N. TAN ,  Yu-Jin CHEN ,  Van H. LE ,  Pei-Hua WANG ,  Bernhard SELL

IPC: H01L27/108 ,  H01L23/528 ,  H01L23/522 ,  H01L49/02

Abstract: Embodiments herein describe techniques for a memory device including at least two memory cells. A first memory cell includes a first storage cell and a first transistor to control access to the first storage cell. A second memory cell includes a second storage cell and a second transistor to control access to the second storage cell. A shared contact electrode is shared between the first transistor and the second transistor, the shared contact electrode being coupled to a source area or a drain area of the first transistor, coupled to a source area or a drain area of the second transistor, and further being coupled to a bit line of the memory device. Other embodiments may be described and/or claimed.

公开(公告)号：US20210098373A1

公开(公告)日：2021-04-01

申请号：US16583691

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Juan G. ALZATE VINASCO ,  Chieh-Jen KU ,  Shem O. OGADHOH ,  Allen B. GARDINER ,  Blake C. LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522

Abstract: Integrated circuit structures having differentiated interconnect lines in a same dielectric layer, and methods of fabricating integrated circuit structures having differentiated interconnect lines in a same dielectric layer, are described. In an example, an integrated circuit structure includes an inter-layer dielectric (ILD) layer above a substrate. A plurality of conductive interconnect lines is in the ILD layer. The plurality of conductive interconnect lines includes a first interconnect line having a first height, and a second interconnect line immediately laterally adjacent to but spaced apart from the first interconnect line, the second interconnect line having a second height less than the first height.

公开(公告)号：US20200303520A1

公开(公告)日：2020-09-24

申请号：US16361881

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Chieh-Jen KU ,  Bernhard SELL ,  Pei-Hua WANG ,  Nikhil MEHTA ,  Shu ZHOU ,  Jared STOEGER ,  Allen B. GARDINER ,  Akash GARG ,  Shem OGADHOH ,  Vinaykumar HADAGALI ,  Travis W. LAJOIE

IPC: H01L29/66 ,  H01L27/108 ,  H01L29/786

Abstract: An integrated circuit structure comprises one or more backend-of-line (BEOL) interconnects formed over a first ILD layer. An etch stop layer is over the one or more BEOL interconnects, the etch stop layer having a plurality of vias that are in contact with the one or more BEOL interconnects. An array of BEOL thin-film-transistors (TFTs) is over the etch stop layer, wherein adjacent ones of the BEOL TFTs are separated by isolation trench regions. The TFTs are aligned with at least one of the plurality of vias to connect to the one or more BEOL interconnects, wherein each of the BEOL TFTs comprise a bottom gate electrode, a gate dielectric layer over the bottom gate electrode, and an oxide-based semiconductor channel layer over the bottom gate electrode having source and drain regions therein. Contacts are formed over the source and drain regions of each of BEOL TFTs, wherein the contacts have a critical dimension of 35 nm or less, and wherein the BEOL TFTs have an absence of diluted hydro-fluoride (DHF).

公开(公告)号：US20200243376A1

公开(公告)日：2020-07-30

申请号：US16260632

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Chieh-Jen KU ,  Bernhard SELL ,  Pei-Hua WANG ,  Harish GANAPATHY ,  Leonard C. PIPES

IPC: H01L21/762 ,  H01L27/108

Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.

公开(公告)号：US20230326860A1

公开(公告)日：2023-10-12

申请号：US18206539

申请日：2023-06-06

Applicant: Intel Corporation

Inventor： Bernhard SELL ,  Oleg GOLONZKA

IPC: H01L23/535 ,  H01L23/485 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L29/49 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/08 ,  H01L29/78 ,  H01L23/532 ,  H01L29/417 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an ILD disposed on a top surface of a metal gate disposed on the substrate.

公开(公告)号：US20230013575A1

公开(公告)日：2023-01-19

申请号：US17956763

申请日：2022-09-29

Applicant: Intel Corporation

Inventor： Bernhard SELL

IPC: H01L29/78 ,  H01L27/108 ,  H01L29/786 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L27/12 ,  H01L27/092 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

Abstract: Semiconductor devices having necked semiconductor bodies and methods of forming semiconductor bodies of varying width are described. For example, a semiconductor device includes a semiconductor body disposed above a substrate. A gate electrode stack is disposed over a portion of the semiconductor body to define a channel region in the semiconductor body under the gate electrode stack. Source and drain regions are defined in the semiconductor body on either side of the gate electrode stack. Sidewall spacers are disposed adjacent to the gate electrode stack and over only a portion of the source and drain regions. The portion of the source and drain regions under the sidewall spacers has a height and a width greater than a height and a width of the channel region of the semiconductor body.

公开(公告)号：US20220320275A1

公开(公告)日：2022-10-06

申请号：US17848224

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen B. GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L29/06 ,  H01L27/12 ,  H01L27/105 ,  H01L21/02 ,  H01L29/423 ,  H01L21/764 ,  H01L21/768

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

公开(公告)号：US20200235249A1

公开(公告)日：2020-07-23

申请号：US16650321

申请日：2017-12-27

Applicant: Intel Corporation

Inventor： Ayan KAR ,  Kinyip PHOA ,  Justin S. SANDFORD ,  Junjun WAN ,  Akm A. AHSAN ,  Leif R. PAULSON ,  Bernhard SELL

IPC: H01L29/94 ,  H01L29/66 ,  H01L29/8605

Abstract: This disclosure illustrates a FinFET based dual electronic component that may be used as a capacitor or a resistor and methods to manufacture said component. A FinFET based dual electronic component comprises a fin, source and drain regions, a gate dielectric, and a gate. The fin is heavily doped such that semiconductor material of the fin becomes degenerate.

公开(公告)号：US20230317720A1

公开(公告)日：2023-10-05

申请号：US18207065

申请日：2023-06-07

Applicant: Intel Corporation

Inventor： Guannan LIU ,  Akm A. AHSAN ,  Mark ARMSTRONG ,  Bernhard SELL

IPC: H01L27/07 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/088

CPC classification number: H01L27/0705 ,  H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/16 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/0847 ,  H01L27/0886 ,  H01L21/823456

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.

公开(公告)号：US20230200043A1

公开(公告)日：2023-06-22

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Van H. LE ,  Chieh-Jen KU ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI ,  Gregory GEORGE ,  Akash GARG ,  Julie ROLLINS ,  Allen B. GARDINER ,  Shem OGADHOH ,  Juan G. ALZATE VINASCO ,  Umut ARSLAN ,  Fatih HAMZAOGLU ,  Nikhil MEHTA ,  Yu-Wen HUANG ,  Shu ZHOU

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.