公开(公告)号：US20220084931A1

公开(公告)日：2022-03-17

申请号：US17537406

申请日：2021-11-29

Applicant: Intel Corporation

Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Brandon RAWLINGS ,  Johanna SWAN

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

Abstract: A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.