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    ZERO-MISALIGNMENT TWO-VIA STRUCTURES
    1.
    发明申请
    ZERO-MISALIGNMENT TWO-VIA STRUCTURES 审中-公开

    公开(公告)号：US20200294901A1

    公开(公告)日：2020-09-17

    申请号：US16649578

    申请日：2017-12-30

    Applicant: Intel Corporation

    Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Brandon RAWLINGS ,  Johanna SWAN

    IPC: H01L23/498 ,  H01L23/48 ,  H01L23/538 ,  H01L21/48

    Abstract: Device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS directly coupled to the interconnect. The ZM2VS further includes the dielectric on a conductive pad, a first via on a first seed, and first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS also has a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

    SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES
    3.
    发明申请
    SKIP LEVEL VIAS IN METALLIZATION LAYERS FOR INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20230130935A1

    公开(公告)日：2023-04-27

    申请号：US18088476

    申请日：2022-12-23

    Applicant: Intel Corporation

    Inventor： Adel ELSHERBINI ,  Mauro KOBRINSKY ,  Shawna LIFF ,  Johanna SWAN ,  Gerald PASDAST ,  Sathya Narasimman TIAGARAJ

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

    Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.

    MULTIPLEXER AND COMBINER STRUCTURES EMBEDDED IN A MMWAVE CONNECTOR INTERFACE
    4.
    发明申请
    MULTIPLEXER AND COMBINER STRUCTURES EMBEDDED IN A MMWAVE CONNECTOR INTERFACE 有权

    公开(公告)号：US20210194106A1

    公开(公告)日：2021-06-24

    申请号：US17194022

    申请日：2021-03-05

    Applicant: Intel Corporation

    Inventor： Telesphor KAMGAING ,  Sasha OSTER ,  Georgios DOGIAMIS ,  Johanna SWAN

    IPC: H01P5/08 ,  H01P1/207 ,  H01P3/12

    Abstract: Embodiments of the invention include a mm-wave waveguide connector and methods of forming such devices. In an embodiment the mm-wave waveguide connector may include a plurality of mm-wave launcher portions, and a plurality of ridge based mm-wave filter portions each communicatively coupled to one of the mm-wave launcher portions. In an embodiment, the ridge based mm-wave filter portions each include a plurality of protrusions that define one or more resonant cavities. Additional embodiments may include a multiplexer portion communicatively coupled to the plurality of ridge based mm-wave filter portions and communicative coupled to a mm-wave waveguide bundle. In an embodiment the plurality of protrusions define resonant cavities with openings between 0.5 mm and 2.0 mm, the plurality of protrusions are spaced apart from each other by a spacing between 0.5 mm and 2.0 mm, and wherein the plurality of protrusions have a thickness between 200 μm and 1,000 μm.

    ZERO-MISALIGNMENT TWO-VIA STRUCTURES
    5.
    发明申请
    ZERO-MISALIGNMENT TWO-VIA STRUCTURES 有权

    公开(公告)号：US20220084931A1

    公开(公告)日：2022-03-17

    申请号：US17537406

    申请日：2021-11-29

    Applicant: Intel Corporation

    Inventor： Veronica STRONG ,  Aleksandar ALEKSOV ,  Brandon RAWLINGS ,  Johanna SWAN

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/48 ,  H01L23/538

    Abstract: A device package and a method of forming a device package are described. The device package includes an interposer with interconnects on an interconnect package layer and a conductive layer on the interposer. The device package has dies on the conductive layer, where the package layer includes a zero-misalignment two-via stack (ZM2VS) and a dielectric. The ZM2VS is directly coupled to the interconnect. The ZM2VS may further include the dielectric on a conductive pad, a first via on a first seed, and the first seed on a top surface of the conductive pad, where the first via extends through dielectric. The ZM2VS may also have a conductive trace on dielectric, and a second via on a second seed, the second seed is on the dielectric, where the conductive trace connects to first and second vias, where second via connects to an edge of conductive trace opposite from first via.

    MMWAVE DIELECTRIC WAVEGUIDE INTERCONNECT TOPOLOGY FOR AUTOMOTIVE APPLICATIONS
    6.
    发明申请
    MMWAVE DIELECTRIC WAVEGUIDE INTERCONNECT TOPOLOGY FOR AUTOMOTIVE APPLICATIONS 审中-公开

    公开(公告)号：US20200168972A1

    公开(公告)日：2020-05-28

    申请号：US16613070

    申请日：2017-07-01

    Applicant: Intel Corporation

    Inventor： Georgios DOGIAMIS ,  Sasha OSTER ,  Telesphor KAMGAING ,  Erich EWY ,  Kenneth SHOEMAKER ,  Adel ELSHERBINI ,  Johanna SWAN

    IPC: H01P3/16 ,  B60W40/02 ,  B60R16/023 ,  B60R11/04

    Abstract: Embodiments of the invention include autonomous vehicles and mm-wave systems for communication between components. In an embodiment the vehicle includes an electronic control unit (ECU). The ECU may include a printed circuit board (PCB) and a CPU die packaged on a CPU packaging substrate. In an embodiment, the CPU packaging substrate is electrically coupled to the PCB. The ECU may also include an external predefined interface electrically coupled to the CPU die. In an embodiment, an active mm-wave interconnect may include a dielectric waveguide, and a first connector coupled to a first end of the dielectric waveguide. In an embodiment, the first connector comprises a first mm-wave engine, and the first connector is electrically coupled to the external predefined interface. Embodiments may also include a second connector coupled to a second end of the dielectric waveguide, wherein the second connector comprises a second mm-wave engine.

    ACCELEROMETER AND METHOD OF MAKING SAME
    8.
    发明申请
    ACCELEROMETER AND METHOD OF MAKING SAME 审中-公开
    加速度计及其制作方法

    公开(公告)号：US20160245841A1

    公开(公告)日：2016-08-25

    申请号：US15051856

    申请日：2016-02-24

    Applicant: Intel Corporation

    Inventor： Qing MA ,  Valluri RAO ,  Feras EID ,  Kevin LIN ,  Weng Hong TEH ,  Johanna SWAN ,  Robert SANKMAN

    IPC: G01P15/097

    CPC classification number: G01P15/097 ,  G01P15/105 ,  G01P15/18

    Abstract: An accelerometer includes a mass, suspended by a beam, and associated conductive paths. Each conductive path is subjected to a magnetic field, such that, when a time varying signal is applied to the conductive paths, a characteristic resonant frequency is produced, and when the mass experiences an acceleration, a respective change in the resonant frequency is produced that may be interpreted as acceleration data. Embodiments include methods of manufacturing an accelerometer and systems and devices incorporating the accelerometer.

    Abstract translation: 加速度计包括由梁悬挂的质量块和相关联的导电路径。 每个导电路径受到磁场的影响，使得当对导电路径施加时变信号时，产生特性谐振频率，并且当质量经历加速度时，产生谐振频率的相应变化， 可以解释为加速度数据。 实施例包括制造加速度计的方法和结合有加速度计的系统和装置。

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