公开(公告)号：US20250110294A1

公开(公告)日：2025-04-03

申请号：US18479012

申请日：2023-09-30

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini

IPC: G02B6/42

Abstract: Technologies for an optical interposer with actuator beams are disclosed. In one embodiment, an integrated circuit package includes an optical interposer and a photonics integrated circuit (PIC) die. The optical interposer includes actuator beams and waveguides embedded in the actuator beams. An electrical trace is disposed on the actuator beams. In use, current can pass through the electrical trace, expanding the trace through thermal expansion. The trace expands more than the actuator beam underneath it, causing the actuator beam and the waveguides to be deflected. In this manner, the waveguides in the optical interposer can be positioned to align to waveguides in the PIC die.

公开(公告)号：US12176676B2

公开(公告)日：2024-12-24

申请号：US17076443

申请日：2020-10-21

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu

IPC: H01S3/04 ,  H01S5/023 ,  H01S5/024 ,  H01S5/042

Abstract: Embodiments disclosed herein include dual sided cooling architectures for laser packages. In an embodiment, an electronic package comprises a package substrate, and a laser chip attached to the package substrate. In an embodiment, the laser chip has a first surface and a second surface opposite from the first surface. In an embodiment, an interposer is disposed over the laser chip, where the interposer overhangs an edge of the laser chip. In an embodiment, the electronic package further comprises an interconnect between the interposer and the package substrate.

公开(公告)号：US20240329313A1

公开(公告)日：2024-10-03

申请号：US18194147

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini ,  Xiaoqian Li

IPC: G02B6/26

CPC classification number: G02B6/26

Abstract: Technologies for optical coupling to photonic integrated circuit (PIC) dies are disclosed. In one illustrative embodiment, a PIC die has one or more waveguides. A lens array is positioned adjacent the PIC die. Light from waveguides of the PIC die reflects off of a reflective surface of the lens array. The reflective surface directs the light from the PIC die towards lenses in the lens array. The lenses collimate the light, facilitating coupling of light to and from other components. The reflective surface on the lens array may be oriented at any suitable angle, resulting in a collimated beam of light that is oriented at any suitable angle.

公开(公告)号：US12107042B2

公开(公告)日：2024-10-01

申请号：US17972340

申请日：2022-10-24

Applicant: Intel Corporation

Inventor： Robert Starkston ,  Debendra Mallik ,  John S. Guzek ,  Chia-Pin Chiu ,  Deepak Kulkarni ,  Ravi V. Mahajan

IPC: H01L23/48 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L25/18

CPC classification number: H01L23/5226 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/14 ,  H01L25/0655 ,  H01L25/50 ,  H01L21/563 ,  H01L24/05 ,  H01L24/13 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05541 ,  H01L2224/05568 ,  H01L2224/0603 ,  H01L2224/131 ,  H01L2224/1403 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/83102 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2224/83102 ,  H01L2924/00014 ,  H01L2224/05541 ,  H01L2924/206 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough.

公开(公告)号：US12009321B2

公开(公告)日：2024-06-11

申请号：US17131863

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Zhen Zhou ,  Tae Young Yang ,  Tolga Acikalin ,  Johanny Escobar Pelaez ,  Kenneth P. Foust ,  Chia-Pin Chiu ,  Renzhi Liu ,  Cheng-Yuan Chin

IPC: H01L23/66 ,  H01L23/14 ,  H01L29/93 ,  H01Q1/22 ,  H01Q1/42 ,  H01Q15/00 ,  H01Q15/14

CPC classification number: H01L23/66 ,  H01L23/14 ,  H01L29/93 ,  H01Q1/2283 ,  H01Q1/422 ,  H01Q15/002 ,  H01Q15/0026 ,  H01Q15/147 ,  H01L2223/6627 ,  H01L2223/6677

Abstract: In various aspects, a package system includes at least a first package and a second package arranged on a same side of the package carrier. Each of the first package and the second package comprises an antenna to transmit and/or receive radio frequency signals. A cover may be arranged at a distance over the first package and the second package at the same side of the package carrier as the first package and the second package. The cover comprises at least one conductive element forming a predefined pattern on a side of the cover facing the first package and the second package. The predefined pattern is configured as a frequency selective surface. The package system further includes a radio frequency signal interface wirelessly connecting the antennas of the first package and the second package. The radio frequency signal interface comprises the at least one conductive element.

公开(公告)号：US20230358952A1

公开(公告)日：2023-11-09

申请号：US17740068

申请日：2022-05-09

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Kaveh Hosseini ,  Omkar G. Karhade

IPC: G02B6/12

CPC classification number: G02B6/12007 ,  G02B2006/12061 ,  G02B6/29338

Abstract: A reduced bridge structure for a photonic integrated circuit (PIC) or any integrated circuit comprising a ring resonator structure. The reduced bridge structure is an architecture including an optical and electrical routing arrangement to reduce the number of bridges around the micro-ring structure of the ring resonator structure. Embodiments reserve one bridge portion for use as a signal trace, not routing the signal trace over a silicon waveguide. By not routing the signal trace over a silicon waveguide, the structure avoids possible interference between the radio frequency (RF) signal on the signal trace and optical communication (a light wave) propagating in the silicon waveguide.

公开(公告)号：US11579426B2

公开(公告)日：2023-02-14

申请号：US16643158

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Anna M. Prakash

IPC: G02B19/00 ,  G02B27/30

Abstract: Aspects of the embodiments are directed to an opto-electronic device and methods of using the same. The opto-electronic device can include a processing device and a photonic device. The photonic device can include an optical demultiplexer; a collimating lens optically coupled to the optical demultiplexer and positioned to receive light from the optical demultiplexer, the collimating lens to collimate light received from the optical demultiplexer; a photodetector comprising a photosensitive element, the photosensitive element to convert received light into an electrical signal; and a focusing lens optically coupled to the photodetector, the focusing lens to receive light and focus the light towards the photosensitive element.

公开(公告)号：US11515232B2

公开(公告)日：2022-11-29

申请号：US16379619

申请日：2019-04-09

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Robert Sankman ,  Pooya Tadayon

IPC: H01L23/473 ,  H05K7/20 ,  H01L23/373 ,  H01L23/367 ,  H01L23/00

Abstract: Embodiments include semiconductor packages and cooling semiconductor packaging systems. A semiconductor package includes a second die on a package substrate, first dies on the second die, conductive bumps between the first dies and the second die, a cold plate and a manifold over the first dies, second die, and package substrate, and first openings in the manifold. The first openings are fluidly coupled through the conductive bumps. The semiconductor package may include a first fluid path through the first openings of the manifold, where a first fluid flows through the first fluid path. The semiconductor package may further include a second fluid path through second openings of the cold plate, where a second fluid flows through the second fluid path, and where the first and second fluids of the first and second fluid paths cool heat providing surfaces of the first dies, the second die, or the package substrate.

公开(公告)号：US11456232B2

公开(公告)日：2022-09-27

申请号：US16100406

申请日：2018-08-10

Applicant: Intel Corporation

Inventor： Zhimin Wan ,  Je-Young Chang ,  Chia-Pin Chiu ,  Shankar Devasenathipathy ,  Betsegaw Kebede Gebrehiwot ,  Chandra Mohan Jha

IPC: H01L23/427 ,  H01L25/18

Abstract: Disclosed herein are thermal assemblies for multi-chip packages (MCPs), as well as related methods and devices. For example, in some embodiments, a thermal assembly for an MCP may include a heat pipe having a ring shape.

公开(公告)号：US20200348498A1

公开(公告)日：2020-11-05

申请号：US16643158

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Anna M. Prakash

IPC: G02B19/00 ,  G02B27/30

Abstract: Aspects of the embodiments are directed to an opto-electronic device and methods of using the same. The opto-electronic device can include a processing device and a photonic device. The photonic device can include an optical demultiplexer; a collimating lens optically coupled to the optical demultiplexer and positioned to receive light from the optical demultiplexer, the collimating lens to collimate light received from the optical demultiplexer; a photodetector comprising a photosensitive element, the photosensitive element to convert received light into an electrical signal; and a focusing lens optically coupled to the photodetector, the focusing lens to receive light and focus the light towards the photosensitive element.