公开(公告)号：US20210408289A1

公开(公告)日：2021-12-30

申请号：US16914145

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Brian Greene ,  Robin Chao ,  Adam Faust ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

Abstract: A transistor structure includes a first channel layer over a second channel layer, where the first and the second channel layers include monocrystalline silicon. An epitaxial source material is coupled to a first end of the first and second channel layers. An epitaxial drain material is coupled to a second end of the first and second channel layers, a gate electrode is between the epitaxial source material and the epitaxial drain material, and around the first channel layer and around the second channel layer. The transistor structure further includes a first gate dielectric layer between the gate electrode and each of the first channel layer and the second channel layer, where the first gate dielectric layer has a first dielectric constant. A second gate dielectric layer is between the first gate dielectric layer and the gate electrode, where the second gate dielectric layer has a second dielectric constant.

公开(公告)号：US12272737B2

公开(公告)日：2025-04-08

申请号：US18368428

申请日：2023-09-14

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  William Hsu ,  Chung-Hsun Lin ,  Kinyip Phoa ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L29/423 ,  H01L27/088 ,  H01L29/417 ,  H01L29/786

Abstract: Gate-all-around integrated circuit structures having adjacent structures for sub-fin electrical contact are described. For example, an integrated circuit structure includes a semiconductor island on a semiconductor substrate. A vertical arrangement of horizontal nanowires is above a fin protruding from the semiconductor substrate. A channel region of the vertical arrangement of horizontal nanowires is electrically isolated from the fin. The fin is electrically coupled to the semiconductor island. A gate stack is over the vertical arrangement of horizontal nanowires.

公开(公告)号：US12166031B2

公开(公告)日：2024-12-10

申请号：US17131616

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Biswajeet Guha ,  Brian Greene ,  Daniel Schulman ,  William Hsu ,  Chung-Hsun Lin ,  Curtis Tsai ,  Kevin Fischer

IPC: H01L27/02 ,  H01L23/60 ,  H01L29/87

Abstract: Substrate-less electrostatic discharge (ESD) integrated circuit structures, and methods of fabricating substrate-less electrostatic discharge (ESD) integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a first fin and a second fin protruding from a semiconductor pedestal. An N-type region is in the first and second fins. A P-type region is in the semiconductor pedestal. A P/N junction is between the N-type region and the P-type region, the P/N junction on or in the semiconductor pedestal.

公开(公告)号：US11869987B2

公开(公告)日：2024-01-09

申请号：US17860056

申请日：2022-07-07

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/93 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/93 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/66174

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.

公开(公告)号：US20230071699A1

公开(公告)日：2023-03-09

申请号：US17470993

申请日：2021-09-09

Applicant: Intel Corporation

Inventor： Andrew Smith ,  Brian Greene ,  Seonghyun Paik ,  Omair Saadat ,  Chung-Hsun Lin ,  Tahir Ghani

IPC: H01L29/423 ,  H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238

Abstract: A transistor structure includes a channel region including first sidewall. A gate electrode includes a first layer having a first portion adjacent to the first sidewall and a second portion adjacent to a gate electrode boundary sidewall. The gate electrode includes a second layer between the first and second portions of the first layer. The first layer has a first composition associated with a first work function material, and has a first lateral thickness from the first sidewall. The second layer has a second composition associated with a second work function material. Depending one a second lateral thickness of the second layer, the second layer may modulate a threshold voltage (VT) of the transistor structure by more or less. In some embodiments, a ratio of the second lateral thickness to the first lateral thickness is less than three.

公开(公告)号：US20250169130A1

公开(公告)日：2025-05-22

申请号：US18515626

申请日：2023-11-21

Applicant: Intel Corporation

Inventor： Tao Chu ,  Minwoo Jang ,  Yanbin Luo ,  Paul Packan ,  Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Feng Zhang ,  Ting-Hsiang Hung ,  Chia-Ching Lin ,  Yang Zhang ,  Kan Zhang ,  Chung-Hsun Lin ,  Anand S. Murthy

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66

Abstract: Fabrication methods for integrated circuit (IC) structures and devices with different nanoribbon thicknesses are disclosed. In one example, an IC structure includes a stack of nanoribbons stacked above one another over the support, including a first nanoribbon with a first channel region and a second nanoribbon with a second channel region, where the first channel region has a first thickness and the second channel region has a second thickness, and where the first thickness of the first channel region is different (e.g., greater) than the second thickness of the second channel region.

公开(公告)号：US12294006B2

公开(公告)日：2025-05-06

申请号：US16727370

申请日：2019-12-26

Applicant: Intel Corporation

Inventor： Chung-Hsun Lin ,  Biswajeet Guha ,  William Hsu ,  Stephen Cea ,  Tahir Ghani

IPC: H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.

公开(公告)号：US20240334669A1

公开(公告)日：2024-10-03

申请号：US18129717

申请日：2023-03-31

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Akitomo Matsubayashi ,  Brian Greene ,  Chung-Hsun Lin

IPC: H10B10/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L27/0886 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785

Abstract: An apparatus comprising a source or drain of a field effect transistor (FET), a first dielectric between a portion of the source or drain and a FET gate, the first dielectric comprising silicon nitride, and a second dielectric above at least a portion of the first dielectric, the second dielectric comprising silicon oxide doped with at least one of oxygen or carbon, the second dielectric having a dielectric constant lower than the first dielectric.

公开(公告)号：US20240290835A1

公开(公告)日：2024-08-29

申请号：US18174007

申请日：2023-02-24

Applicant: Intel Corporation

Inventor： Chiao-Ti Huang ,  Guowei Xu ,  Tao Chu ,  Robin Chao ,  Jaladhi Mehta ,  Brian Greene ,  Chung-Hsun Lin

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/40 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L27/0886 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/78696

Abstract: Fabrication methods that employ an etch stop layer to assist subfin removal during fabrication of nanoribbon-based transistors are disclosed. An example fabrication method includes providing a stack of nanoribbons above a subfin, where the nanoribbons and the subfin include one or more semiconductor materials; depositing an etch stop layer over a top of the subfin and around portions of the nanoribbons; removing the etch stop layer from around the portions of the nanoribbons; providing a gate dielectric material around the portions of the nanoribbons and over the etch stop layer over the top of the subfin; depositing a gate electrode material around the portions of the nanoribbons; and performing an etch to remove the subfin without substantially removing the etch stop layer.

公开(公告)号：US11417781B2

公开(公告)日：2022-08-16

申请号：US16830112

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Ayan Kar ,  Saurabh Morarka ,  Carlos Nieva-Lozano ,  Kalyan Kolluru ,  Biswajeet Guha ,  Chung-Hsun Lin ,  Brian Greene ,  Tahir Ghani

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.