公开(公告)号：US20190304889A1

公开(公告)日：2019-10-03

申请号：US15941903

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Meizi JIAO ,  Chong ZHANG ,  Hongxia FENG ,  Kevin MCCARTHY

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H05K1/11 ,  H05K3/40 ,  H05K3/06

Abstract: Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.

公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20230317706A1

公开(公告)日：2023-10-05

申请号：US17710753

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Kuang LIU ,  Bohan SHAN ,  Hongxia FENG ,  Don Douglas JOSEPHSON ,  Stephen MOREIN ,  Kaladhar RADHAKRISHNAN

IPC: H01L25/18 ,  H01L23/373 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L23/3736 ,  H01L25/0652 ,  H01L24/40 ,  H01L23/538 ,  H01L21/4871 ,  H01L24/37 ,  H01L2224/37147 ,  H01L24/83 ,  H01L2224/83385 ,  H01L2224/83447 ,  H01L24/33 ,  H01L2224/3303 ,  H01L24/06 ,  H01L2224/0603 ,  H01L2224/32258 ,  H01L2224/4046 ,  H01L24/32 ,  H01L2224/40499 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.

公开(公告)号：US20230098501A1

公开(公告)日：2023-03-30

申请号：US17485375

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Sarah BLYTHE ,  Jieying KONG ,  Peumie ABEYRATNE KURAGAMA ,  Hongxia FENG

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/532

Abstract: A system includes a metallic contact integrated onto a semiconductor integrated circuit substrate with a stress buffer dielectric between the contact and the bulk dielectric. The bulk dielectric typically covers an integrated circuit metal layer to provide electrical isolation of the circuitry. The semiconductor circuit can include a trace that connects the contact to a package pad to enable external access to the signal from off the semiconductor circuit. The stress buffer dielectric has higher elongation and lower filler loading relative to the bulk dielectric, which makes the stress buffer more pliable. The stress buffer is disposed between the contact and the bulk dielectric to improve stress response, reducing the possibility of delamination of the contact from the bulk dielectric.

公开(公告)号：US20190295937A1

公开(公告)日：2019-09-26

申请号：US15927047

申请日：2018-03-20

Applicant: Intel Corporation

Inventor： Chong ZHANG ,  Ying WANG ,  Cheng XU ,  Hongxia FENG ,  Meizi JIAO ,  Junnan ZHAO ,  Yikang DENG

IPC: H01L23/498 ,  C23C18/26 ,  H05K1/11 ,  H01L23/00 ,  H01L21/48

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a trace disposed on a conductive layer. The semiconductor package has one or more adhesion anchoring points and a plurality of portions on the trace. An adhesion anchoring point is between two portions on the trace. A surface roughness of an adhesion anchoring point is greater than a surface roughness of a portion on the trace. The trace may be a high-speed input/output (HSIO) trace. The semiconductor package may include via pads disposed on each end of the trace, and a dielectric disposed on the trace. The dielectric is patterned to form openings on the dielectric that expose second portions on the trace. The dielectric remains over the portions. The semiconductor package may have a chemical treatment disposed on the exposed openings on the trace to form the adhesion anchoring points.

公开(公告)号：US20190027431A1

公开(公告)日：2019-01-24

申请号：US15654399

申请日：2017-07-19

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Dingying David XU ,  Sheng C. LI ,  Matthew L. TINGEY ,  Meizi JIAO ,  Chung Kwang Christopher TAN

IPC: H01L23/498 ,  H01L23/13 ,  H01L21/48

Abstract: A package substrate and package assembly including a package substrate including a substrate body including electrical routing features therein and a surface layer and a plurality of first and second contact points on the surface layer including a first pitch and a second pitch, respectively, wherein the plurality of first contact points and the plurality of second contact points are continuous posts to the respective ones of the electrical routing features. A method including forming first conductive vias in a package assembly, wherein the first conductive vias include substrate conductive vias to electrical routing features in a package substrate and bridge conductive vias to bridge surface routing features of a bridge substrate; forming a first surface layer and a second surface layer on the package substrate; and forming second conductive vias through each of the first surface layer and the second surface layer to the bridge conductive vias.

公开(公告)号：US20250113434A1

公开(公告)日：2025-04-03

申请号：US18374617

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Bai NIE ,  Mitchell PAGE ,  Junxin WANG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Haifa HARIRI ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Hongxia FENG ,  Haobo CHEN ,  Bohan SHAN ,  Hiroki TANAKA ,  Leonel R. ARANA ,  Yonggang Yong LI

IPC: H05K1/02 ,  H01L23/15 ,  H01L23/498 ,  H05K1/03 ,  H05K1/11

Abstract: Embodiments disclosed herein include package substrates with a glass core. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface, and the substrate is a solid glass layer. In an embodiment, an opening is provided through a thickness of the substrate, where the opening comprises a sidewall that is non-orthogonal with the first surface of the substrate. In an embodiment a corner at a junction between the sidewall and the first surface is rounded. In an embodiment, a via is provided in the opening, where the via is electrically conductive.

公开(公告)号：US20250112164A1

公开(公告)日：2025-04-03

申请号：US18374932

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Onur OZKAN ,  Ryan CARRAZZONE ,  Rui ZHANG ,  Haobo CHEN ,  Ziyin LIN ,  Yiqun BAI ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Venkata Rajesh SARANAM ,  Shripad GOKHALE ,  Kartik SRINIVASAN ,  Edvin CETEGEN ,  Mine KAYA ,  Nicholas S. HAEHN ,  Deniz TURAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.

公开(公告)号：US20230317653A1

公开(公告)日：2023-10-05

申请号：US17709367

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Hongxia FENG ,  Xiaoxuan SUN ,  Amey Anant APTE ,  Dingying David XU ,  Sairam AGRAHARAM ,  Gang DUAN ,  Ashay DANI

IPC: H01L23/00 ,  H01L25/10 ,  H01L25/00

CPC classification number: H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L25/105 ,  H01L25/50 ,  H01L24/80 ,  H01L2224/80379 ,  H01L2224/8049 ,  H01L2924/07025 ,  H01L2224/0557 ,  H01L2224/05647 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/13025 ,  H01L24/13 ,  H01L24/03 ,  H01L2224/03845 ,  H01L2224/94 ,  H01L24/94 ,  H01L2224/80855 ,  H01L2224/80201 ,  H01L2225/1023 ,  H01L2225/1047

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.

公开(公告)号：US20210366860A1

公开(公告)日：2021-11-25

申请号：US16880483

申请日：2020-05-21

Applicant: Intel Corporation

Inventor： Jung Kyu HAN ,  Hongxia FENG ,  Xiaoying GUO ,  Rahul N. MANEPALLI

IPC: H01L23/00 ,  H01L23/538

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and a bridge substrate embedded in the package substrate. In an embodiment, first pads are over the package substrate, where the first pads have a first pitch, and second pads are over the bridge substrate, where the second pads have a second pitch that is smaller than the first pitch. In an embodiment, a barrier layer is over individual ones of the second pads. In an embodiment, reflown solder is over individual ones of the first pads and over individual ones of the second pads. In an embodiment, a first standoff height of the reflown solder over the first pads is equal to a second standoff height of the reflown solder over the second pads.