公开(公告)号：US20220102892A1

公开(公告)日：2022-03-31

申请号：US17032587

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Srikant Nekkanty ,  Steven Klein ,  Feroz Mohammad ,  Joe Walczyk ,  Kuang Liu ,  Zhichao Zhang

IPC: H01R13/11 ,  H05K1/02 ,  H05K9/00

Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.

公开(公告)号：US20210239734A1

公开(公告)日：2021-08-05

申请号：US17174191

申请日：2021-02-11

Applicant: Intel Corporation

Inventor： Joe Walczyk ,  Pooya Tadayon

IPC: G01R1/067 ,  G01R3/00 ,  B81B7/02 ,  H01L23/00 ,  G01R31/26

Abstract: A device probe includes a primary probe arm and a subsequent probe arm with a slip plane spacing between the primary probe arm and subsequent probe arm. Each probe arm is integrally part of a probe base that is attachable to a probe card. During probe use on a semiconductive device or a semiconductor device package substrate, overtravel of the probe tip allows the primary and subsequent probe arms to deflect, while sufficient resistance to deflection creates a useful contact with an electrical structure such as an electrical bump or a bond pad.

公开(公告)号：US20210088554A1

公开(公告)日：2021-03-25

申请号：US17111298

申请日：2020-12-03

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/48 ,  H01L23/32 ,  H01L21/48 ,  H01L21/027 ,  G01R31/28 ,  H01L23/14

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US20190203370A1

公开(公告)日：2019-07-04

申请号：US15857362

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Joe Walczyk ,  Pooya Tadayon ,  Andrew Hoitink ,  Tanner Schulz

IPC: C25D5/02 ,  C25D17/00 ,  H05K3/18 ,  H05K13/00

CPC classification number: C25D5/026 ,  C25D17/00 ,  H05K3/188 ,  H05K13/0015

Abstract: A micronozzle assembly, comprising a reservoir, an array of structures comprising micronozzles, a porous structure positioned between the reservoir and the array, and an electrode within the reservoir, wherein the electrode comprises any of a mesh, a frame along the perimeter of the cavity of the reservoir, or a rod extending into a cavity of the reservoir.

公开(公告)号：US11639556B2

公开(公告)日：2023-05-02

申请号：US15857362

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Joe Walczyk ,  Pooya Tadayon ,  Andrew Hoitink ,  Tanner Schulz

IPC: C25D17/00 ,  C25D5/02 ,  H05K13/00 ,  H05K3/18 ,  C25D1/00

Abstract: A micronozzle assembly, comprising a reservoir, an array of structures comprising micronozzles, a porous structure positioned between the reservoir and the array, and an electrode within the reservoir, wherein the electrode comprises any of a mesh, a frame along the perimeter of the cavity of the reservoir, or a rod extending into a cavity of the reservoir.

公开(公告)号：US20210407877A1

公开(公告)日：2021-12-30

申请号：US16911820

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Joe Walczyk ,  Paul Diglio

IPC: H01L23/31 ,  H01L25/18 ,  H01L25/065 ,  H01L21/56

Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.

公开(公告)号：US20190212366A1

公开(公告)日：2019-07-11

申请号：US15863600

申请日：2018-01-05

Applicant: Intel Corporation

Inventor： Pooya Tadayon ,  Mark Bohr ,  Joe Walczyk

IPC: G01R1/073 ,  H01L23/48 ,  H01L23/32 ,  H01L23/14 ,  H01L21/48 ,  H01L21/027 ,  G01R31/28

CPC classification number: G01R1/07342 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/0273 ,  H01L21/486 ,  H01L23/147 ,  H01L23/32 ,  H01L23/481

Abstract: An electrical-test apparatus is provided, which includes a MEMS array. In an example, the MEMS array comprises a plurality of tester interconnect structures cantilevered from first terminals on a first side of a substrate. The tester interconnect structures may have a first diameter. In an example, the MEMS array comprises a plurality of through-substrate vias that extend through the substrate, the vias having a second diameter larger than the first diameter. In an example, individual ones of the vias electrically couple individual ones of the tester interconnect structures to corresponding ones of second terminals on a second side of the substrate.

公开(公告)号：US10338099B2

公开(公告)日：2019-07-02

申请号：US15626986

申请日：2017-06-19

Applicant: Intel Corporation

Inventor： Christopher Del Barga ,  Joe Walczyk ,  Ronald Michael Kirby

IPC: G01R1/04

Abstract: A socket assembly for a microelectronic device can include a body and a plurality of arm. The body can include a central socket configured to receive a microelectronic device therein. The plurality of arms can each be adjacent to the central socket, where each of the plurality of arms can be rotatably coupled to the body and each of the plurality of arms can be translatable relative to the body to move between an open position and a closed position. The arms can retain a microelectronic device within the central socket when the arms are in the closed position.

公开(公告)号：US20190096785A1

公开(公告)日：2019-03-28

申请号：US15718337

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Joe Walczyk ,  John C. Johnson

IPC: H01L23/427 ,  F28F1/40

Abstract: A heat spreader apparatus, testing system, method may be used to test an electronic device. The heat spreader may include a hollow housing. The hollow housing may define an interior chamber. The hollow housing may include a contact surface. The heat spreader may include a working fluid. The working fluid may be included in the interior chamber. The hollow housing may be configured to be physically compliant. The hollow housing may be physically compliant such that the hollow housing conforms to the shape of a testing surface in response to an applied pressure. The testing surface may be a top surface of a semiconductor. The testing surface may be curved or otherwise lack uniformity. The hollow housing may conform to the curvature or lack of uniformity of the testing surface such that minimal gaps exist between the hollow housing and the surface.

公开(公告)号：US12136577B2

公开(公告)日：2024-11-05

申请号：US16911820

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Joe Walczyk ,  Paul Diglio

IPC: H01L23/31 ,  H01L21/56 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H01L25/18

Abstract: A contiguous integrated heat spreader suitable for an integrated circuit (IC) die package. Heat spreader material may be deposited with a high throughput additive manufacturing (HTAM) technique directly upon a surface of an IC die, and over a portion of a package substrate beyond an edge of the IC die. The contiguous heat spreader may have high thermal conductivity and offer low thermal resistance in absence of any intervening thermal interface material (TIM). The contiguous heat spreader may span multiple IC die and accommodate different die heights. The heat spreader may be contiguous with multiple die. Heat spreader material may be absent where thermal breaks within the heat spreader are advantageous.