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公开(公告)号:US11569596B2
公开(公告)日:2023-01-31
申请号:US16833221
申请日:2020-03-27
Applicant: Intel Corporation
Inventor: Steven A. Klein , Kuang Liu , Srikant Nekkanty , Feroz Mohammad , Donald Tiendung Tran , Srinivasa Aravamudhan , Hemant Mahesh Shah , Alexander W. Huettis
Abstract: Systems, apparatus, and/or processes directed to applying pressure to a socket to alter a shape of the socket to improve a connection between the socket and a substrate, printed circuit board, or other component. The socket may receive one or more chips, may be an interconnect, or may be some other structure that is part of a package. The shape of the socket may be flattened so that a side of the socket may form a high-quality physical and electrical coupling with the substrate.
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公开(公告)号:US11830846B2
公开(公告)日:2023-11-28
申请号:US16424227
申请日:2019-05-28
Applicant: Intel Corporation
Inventor: Feroz Mohammad , Srinivasa R. Aravamudhan
IPC: H01L23/498 , H01L23/00 , H01L23/34
CPC classification number: H01L24/81 , H01L23/345 , H01L23/49811 , H01L24/16 , H01L24/98 , H01L2224/16238 , H01L2224/81234 , H01L2224/81815
Abstract: Embodiments herein relate to systems, apparatuses, or processes for coupling or decoupling two substrates by heating pins on one of the substrates and either inserting or withdrawing the heated pins from solder elements on a BGA. In particular, by heating a plurality of pins on a first side of a first substrate, where the plurality of pins are substantially perpendicular to a plane of the substrate, inserting the heated plurality of pins into BGA attached to a second substrate where the BGA includes a plurality of solder elements aligned with the plurality of pins and where the heated plurality of pins melt the plurality of solder elements upon insertion. The inserted plurality of pins physically and/or electrically couple the first substrate and the second substrate.
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公开(公告)号:US20220102892A1
公开(公告)日:2022-03-31
申请号:US17032587
申请日:2020-09-25
Applicant: Intel Corporation
Inventor: Srikant Nekkanty , Steven Klein , Feroz Mohammad , Joe Walczyk , Kuang Liu , Zhichao Zhang
Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.
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公开(公告)号:US20220102883A1
公开(公告)日:2022-03-31
申请号:US17032595
申请日:2020-09-25
Applicant: Intel Corporation
Inventor: Srikant Nekkanty , Steven Klein , Feroz Mohammad
Abstract: Techniques and mechanisms for coupling packaged devices with a dual-sided socket device. In an embodiment, two interfaces of the socket device comprise, respectively, first metallization structures and second metallization structures on opposite sides of a socket body structure. The first metallization structures each form a respective corrugation structure to electrically couple with a corresponding conductive contact of a first packaged device. The corrugation structures facilitate such electrical coupling each via a vertical wipe of the corresponding conductive contact. In another embodiment, a pitch of the first metallization structures is in a range of between 0.1 millimeters (mm) and 2 mm. One such metallization structure has a vertical span in a range of between 0.05 mm and 2.0 mm, where a portion of a side of the metallization structure forms a corrugation structure, and has a horizontal span which is at least 5% of the vertical span.
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公开(公告)号:US11916322B2
公开(公告)日:2024-02-27
申请号:US17032595
申请日:2020-09-25
Applicant: Intel Corporation
Inventor: Srikant Nekkanty , Steven Klein , Feroz Mohammad
CPC classification number: H01R12/714 , H01R43/26
Abstract: Techniques and mechanisms for coupling packaged devices with a dual-sided socket device. In an embodiment, two interfaces of the socket device comprise, respectively, first metallization structures and second metallization structures on opposite sides of a socket body structure. The first metallization structures each form a respective corrugation structure to electrically couple with a corresponding conductive contact of a first packaged device. The corrugation structures facilitate such electrical coupling each via a vertical wipe of the corresponding conductive contact. In another embodiment, a pitch of the first metallization structures is in a range of between 0.1 millimeters (mm) and 2 mm. One such metallization structure has a vertical span in a range of between 0.05 mm and 2.0 mm, where a portion of a side of the metallization structure forms a corrugation structure, and has a horizontal span which is at least 5% of the vertical span.
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公开(公告)号:US20220069532A1
公开(公告)日:2022-03-03
申请号:US17008979
申请日:2020-09-01
Applicant: Intel Corporation
Inventor: Feroz Mohammad , Steven Klein , Srikant Nekkanty
IPC: H01R33/76 , H01L23/498 , H01L23/32
Abstract: An integrated circuit assembly may be formed comprising an electronic socket having at least one conductive pin, wherein a portion of the conductive pin extends from the electronic socket. The integrated circuit assembly further comprises a conductive interposer including at least one conductive via having a conductive layer on a sidewall thereof. The conductive interposer is abutted against the electronic socket, such that the at least one conductive pin is inserted into the at least one conductive via and is biased against the conductive layer of the at least one conductive via. In further embodiments, an integrated circuit package may be electrically attached to the conductive interposer.
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公开(公告)号:US10355380B1
公开(公告)日:2019-07-16
申请号:US15938110
申请日:2018-03-28
Applicant: Intel Corporation
Inventor: Feroz Mohammad , Srinivasa Aravamudhan
CPC classification number: H01R12/52 , H01R12/716 , H01R12/722 , H05K7/2039
Abstract: An electronic device that includes a first electronic component with a pin element and a second electronic component with a solder element. A joint is formed that provides an electrical and mechanical connection between the first electronic component and second electronic component when the pin element is heated, inserted into the solder element, and cooled.
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公开(公告)号:US12009612B2
公开(公告)日:2024-06-11
申请号:US17032587
申请日:2020-09-25
Applicant: Intel Corporation
Inventor: Srikant Nekkanty , Steven Klein , Feroz Mohammad , Joe Walczyk , Kuang Liu , Zhichao Zhang
CPC classification number: H01R13/11 , H05K1/0213 , H05K9/0022
Abstract: Techniques and mechanisms for coupling packaged devices with a socket device. In an embodiment, the socket device comprises a socket body structure and conductors extending therethrough. A pitch of the conductors is in a range of between 0.1 millimeters (mm) and 3 mm. First and second metallization structures also extend, respectively, from opposite respective sides of the socket body structure. In the socket body structure, a conductive shield structure, electrically coupled to the first and second metallization structures, substantially extends around one of the conductors. For each of the first and second metallization structures, a vertical span of the metallization structure is in a range of between 0.05 mm and 2.0 mm, a portion of a side of the metallization structure forms a respective corrugation structure, and a horizontal span of the portion is at least 5% of the vertical span of the metallization structure.
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公开(公告)号:US11818832B2
公开(公告)日:2023-11-14
申请号:US16828447
申请日:2020-03-24
Applicant: Intel Corporation
Inventor: Feroz Mohammad , Ralph V. Miele , Thomas Boyd , Steven A. Klein , Gregorio R. Murtagian , Eric W. Buddrius , Daniel Neumann , Rolf Laido
CPC classification number: H05K1/0203 , H05K7/20509 , H01L2023/405 , H01L2023/4087 , H01R12/85 , H05K1/181 , H05K2201/10325
Abstract: Embodiments disclosed herein include assemblies. In an embodiment, an assembly comprises a socket and a bolster plate on a board, where the bolster plate has load studs and an opening that surrounds the socket; a shim having first and second ends; and a carrier on the bolster plate, where the carrier has an opening and cutouts. The shim may have an opening through the first end as the second end is affixed to the carrier. The opening of the shim entirely over one cutout from a corner region of the carrier. In an embodiment, the assembly comprises an electronic package in the opening of the carrier, where the electronic package is affixed to the carrier, and a heatsink over the electronic package and carrier, where the first end is directly coupled to a surface of the heatsink and a surface of one load stud of the bolster plate.
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公开(公告)号:US20190305451A1
公开(公告)日:2019-10-03
申请号:US15938110
申请日:2018-03-28
Applicant: Intel Corporation
Inventor: Feroz Mohammad , Srinivasa Aravamudhan
Abstract: An electronic device that includes a first electronic component with a pin element and a second electronic component with a solder element. A joint is formed that provides an electrical and mechanical connection between the first electronic component and second electronic component when the pin element is heated, inserted into the solder element, and cooled.
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