公开(公告)号：US11527532B2

公开(公告)日：2022-12-13

申请号：US16419240

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L23/31 ,  H01L23/00 ,  H01L29/778 ,  H01L25/065

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor-based cascode arrangements that may simultaneously realize enhancement mode transistor operation and high voltage capability. In one aspect, an IC structure includes a source region, a drain region, an enhancement mode III-N transistor, and a depletion mode III-N transistor, where each of the transistors includes a first and a second source or drain (S/D) terminals. The transistors are arranged in a cascode arrangement in that the first S/D terminal of the enhancement mode III-N transistor is coupled to the source region, the second S/D terminal of the enhancement mode III-N transistor is coupled to the first S/D terminal of the depletion mode III-N transistor, and the second S/D terminal of the depletion mode III-N transistor is coupled to the drain region.

公开(公告)号：US20200335526A1

公开(公告)日：2020-10-22

申请号：US16390478

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8258 ,  H01L29/778

Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.

公开(公告)号：US20200227407A1

公开(公告)日：2020-07-16

申请号：US16249256

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Han Wui Then ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Johann Christian Rode ,  Walid M. Hafez

IPC: H01L27/07 ,  H01L49/02 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66 ,  H01L29/423

Abstract: Disclosed herein are IC structures, packages, and devices that include polysilicon resistors, monolithically integrated on the same substrate/die/chip as III-N transistors. An example IC structure includes an III-N semiconductor material provided over a support structure, a III-N transistor provided over a first portion of the III-N material, and a polysilicon resistor provided over a second portion of the III-N material. Because the III-N transistor and the polysilicon resistor are both provided over a single support structure, they may be referred to as “integrated” transistors. Because the III-N transistor and the polysilicon resistor are provided over different portions of the III-N semiconductor material, and, therefore, over different portion of the support structure, their integration may be referred to as “side-by-side” integration.

公开(公告)号：US11848362B2

公开(公告)日：2023-12-19

申请号：US16388479

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann Christian Rode ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/417 ,  H01L29/205 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L29/41775 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7786

Abstract: Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.

公开(公告)号：US11670709B2

公开(公告)日：2023-06-06

申请号：US16297837

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Marko Radosavljevic ,  Han Wui Then ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Paul B. Fischer ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/08 ,  H01L29/04 ,  H01L29/423

CPC classification number: H01L29/7787 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42356 ,  H01L29/66462

Abstract: Disclosed herein are IC structures, packages, and device assemblies with III-N transistors that include additional materials, referred to herein as “stressor materials,” which may be selectively provided over portions of polarization materials to locally increase or decrease the strain in the polarization material. Providing a compressive stressor material may decrease the tensile stress imposed by the polarization material on the underlying portion of the III-N semiconductor material, thereby decreasing the two-dimensional electron gas (2DEG) and increasing a threshold voltage of a transistor. On the other hand, providing a tensile stressor material may increase the tensile stress imposed by the polarization material, thereby increasing the 2DEG and decreasing the threshold voltage. Providing suitable stressor materials enables easier and more accurate control of threshold voltage compared to only relying on polarization material recess.

公开(公告)号：US11581313B2

公开(公告)日：2023-02-14

申请号：US16283301

申请日：2019-02-22

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Johann Christian Rode ,  Han Wui Then ,  Marko Radosavljevic ,  Paul B. Fischer ,  Nidhi Nidhi ,  Rahul Ramaswamy ,  Sandrine Charue-Bakker ,  Walid M. Hafez

IPC: H01L27/092 ,  H01L29/26 ,  H01L21/8238 ,  H01L21/8258 ,  H01L29/267

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors integrated on the same support structure as non-III-N transistors (e.g., Si-based transistors), using semiconductor regrowth. In one aspect, a non-III-N transistor may be integrated with an III-N transistor by depositing a III-N material, forming an opening in the III-N material, and epitaxially growing within the opening a semiconductor material other than the III-N material. Since the III-N material may serve as a foundation for forming III-N transistors, while the non-III-N material may serve as a foundation for forming non-III-N transistors, such an approach advantageously enables implementation of both types of transistors on a single support structure. Proposed integration may reduce costs and improve performance by enabling integrated digital logic solutions for III-N transistors and by reducing losses incurred when power is routed off chip in a multi-chip package.

公开(公告)号：US20200335592A1

公开(公告)日：2020-10-22

申请号：US16388479

申请日：2019-04-18

Applicant: Intel Corporation

Inventor： Rahul Ramaswamy ,  Nidhi Nidhi ,  Walid M. Hafez ,  Johann Christian Rode ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/417 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205

Abstract: Disclosed herein are IC structures, packages, and devices that include transistors, e.g., III-N transistors, having a source region, a drain region (together referred to as “source/drain” (S/D) regions), and a gate stack. In one aspect, a contact to at least one of the S/D regions of a transistor may have a width that is smaller than a width of the S/D region. In another aspect, a contact to a gate electrode material of the gate stack of a transistor may have a width that is smaller than a width of the gate electrode material. Reducing the width of contacts to S/D regions or gate electrode materials of a transistor may reduce the overlap area between various pairs of these contacts, which may, in turn, allow reducing the off-state capacitance of the transistor. Reducing the off-state capacitance of III-N transistors may advantageously allow increasing their switching frequency.

公开(公告)号：US20200335590A1

公开(公告)日：2020-10-22

申请号：US16390819

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Yang Cao ,  Han Wui Then ,  Johann Christian Rode ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Paul B. Fischer

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66

Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistors implementing various means by which their threshold voltage it tuned. In some embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included in a gate stack of the transistor. In other embodiments, a III-N transistor may include a doped semiconductor material or a fixed charge material included between a gate stack and a III-N channel stack of the transistor. Including doped semiconductor or fixed charge materials either in the gate stack or between the gate stack and the III-N channel stack of III-N transistors adds charges, which affects the amount of 2DEG and, therefore, affects the threshold voltages of these transistors.

公开(公告)号：US20200312961A1

公开(公告)日：2020-10-01

申请号：US16367549

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Han Wui Then ,  Nidhi Nidhi ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Samuel Jack Beach ,  Xiaojun Weng ,  Johann Christian Rode ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/10 ,  H01L29/20 ,  H01L29/786 ,  H01L29/778 ,  H01L29/16 ,  H01L29/08 ,  H01L21/8238 ,  H01L27/07

Abstract: Disclosed herein are IC structures, packages, and devices that include thin-film transistors (TFTs) integrated on the same substrate/die/chip as III-N devices, e.g., III-N transistors. In various aspects, TFTs integrated with III-N transistors have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. In various aspects, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks.

公开(公告)号：US12148757B2

公开(公告)日：2024-11-19

申请号：US16390478

申请日：2019-04-22

Applicant: Intel Corporation

Inventor： Nidhi Nidhi ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta ,  Paul B. Fischer ,  Rahul Ramaswamy ,  Walid M. Hafez ,  Johann Christian Rode

IPC: H01L21/00 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/12 ,  H01L29/778

Abstract: Disclosed herein are IC structures, packages, and devices that include Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si transistors or other non-Si-based devices. In some aspects, the Si-based semiconductor material stack may be provided by semiconductor regrowth over an insulator material. Providing a Si-based semiconductor material stack monolithically integrated on the same support structure as non-Si based devices may provide a viable approach to integrating Si-based transistors with non-Si technologies because the Si-based semiconductor material stack may serve as a foundation for forming Si-based transistors.