公开(公告)号：US09612842B2

公开(公告)日：2017-04-04

申请号：US14976231

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

IPC: G06F12/00 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/42

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US09563429B2

公开(公告)日：2017-02-07

申请号：US14975222

申请日：2015-12-18

Applicant: Intel Corporation

Inventor： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

IPC: G06F12/00 ,  G06F9/38 ,  G06F9/30 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80 ,  G06F13/42

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract translation: 根据一个实施例，处理器包括指令解码器，用于解码从存储器收集数据元素的第一指令，所述第一指令具有指定第一存储位置的第一操作数和指定存储多个数据元素的第一存储器地址的第二操作数 。 处理器还包括执行单元，其响应于第一指令而耦合到指令解码器，基于由第二操作数指示的第一存储器地址从存储器位置读取连续的第一和第二数据元素，并且 将所述第一数据元素存储在所述第一存储位置的第一条目中，以及将第二数据元素存储在与所述第一存储位置的所述第一条目相对应的第二存储位置的第二条目中。

公开(公告)号：US11599362B2

公开(公告)日：2023-03-07

申请号：US17316680

申请日：2021-05-10

Applicant: Intel Corporation

Inventor： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/42

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US10275257B2

公开(公告)日：2019-04-30

申请号：US15601003

申请日：2017-05-22

Applicant: Intel Corporation

Inventor： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/42

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20170255470A1

公开(公告)日：2017-09-07

申请号：US15601003

申请日：2017-05-22

Applicant: Intel Corporation

Inventor： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US20160103684A1

公开(公告)日：2016-04-14

申请号：US14976216

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

IPC: G06F9/30 ,  G06F12/08 ,  G06F12/10 ,  G06F15/80

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

公开(公告)号：US10175990B2

公开(公告)日：2019-01-08

申请号：US13898189

申请日：2013-05-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US20180150301A9

公开(公告)日：2018-05-31

申请号：US13898189

申请日：2013-05-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US09804842B2

公开(公告)日：2017-10-31

申请号：US14581535

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Jesus Corbal San Adrian ,  Dennis R. Bradford ,  Benjamin C. Chaffin ,  Taraneh Bahrami ,  Jonathan C. Hall ,  Thomas B. Maciukenas ,  Roger Gramunt ,  Rohan Sharma

IPC: G06F9/302 ,  G06F9/305 ,  G06F9/312 ,  G06F9/315 ,  G06F15/76 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30072 ,  G06F9/30101 ,  G06F15/8084

Abstract: An apparatus and method for efficiently managing the architectural state of a processor. For example, one embodiment of a processor comprises: a source mask register to be logically subdivided into at least a first portion to store a usable portion of a mask value and a second portion to store an indication of whether the usable portion of the mask value has been updated; a control register to store an unusable portion of the mask value; architectural state management logic to read the indication to determine whether the mask value has been updated prior to performing a store operation, wherein if the mask value has been updated, then the architectural state management logic is to read the usable portion of the mask value from the first portion of the source mask register and zero out bits of the unusable portion of the mask value to generate a final mask value to be saved to memory, and wherein if the mask value has not been updated, then the architectural state management logic is to concatenate the usable portion of the mask value with the unusable portion of the mask value read from the control register to generate a final mask value to be saved to memory.

公开(公告)号：US09632792B2

公开(公告)日：2017-04-25

申请号：US14976220

申请日：2015-12-21

Applicant: Intel Corporation

Inventor： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

IPC: G06F12/10 ,  G06F9/38 ,  G06F9/30 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/42

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.