公开(公告)号：US10901871B2

公开(公告)日：2021-01-26

申请号：US16292850

申请日：2019-03-05

Applicant: Intel Corporation

Inventor： Rolf Kuehnis ,  Peter Lachner

IPC: G06F11/34 ,  G06F15/78

Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.

公开(公告)号：US10175990B2

公开(公告)日：2019-01-08

申请号：US13898189

申请日：2013-05-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y. K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/38 ,  G06F9/30 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US20180150301A9

公开(公告)日：2018-05-31

申请号：US13898189

申请日：2013-05-20

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang (Y.K.) Chen ,  Mayank Bomb ,  Jason W. Brandt ,  Mark J. Buxton ,  Mark J. Charney ,  Srinivas Chennupaty ,  Jesus Corbal ,  Martin G. Dixon ,  Milind B. Girkar ,  Jonathan C. Hall ,  Hideki (Saito) Ido ,  Peter Lachner ,  Gilbert Neiger ,  Chris J. Newburn ,  Rajesh S. Parthasarathy ,  Bret L. Toll ,  Robert Valentine ,  Jeffrey G. Wiedemeier

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345

Abstract: According to a first aspect, efficient data transfer operations can be achieved by: decoding by a processor device, a single instruction specifying a transfer operation for a plurality of data elements between a first storage location and a second storage location; issuing the single instruction for execution by an execution unit in the processor; detecting an occurrence of an exception during execution of the single instruction; and in response to the exception, delivering pending traps or interrupts to an exception handler prior to delivering the exception.

公开(公告)号：US09632907B2

公开(公告)日：2017-04-25

申请号：US14566374

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Beeman C. Strong ,  Stephen J. Robinson ,  Jason W. Brandt ,  Peter Lachner

IPC: G06F11/00 ,  G06F11/34 ,  G06F11/36 ,  G06F9/30

CPC classification number: G06F11/3466 ,  G06F9/30 ,  G06F11/3636

Abstract: A processing device implementing tracking of deferred data packets in a debug trace architecture is disclosed. The processing device is to determine an order number corresponding to an order in which an instruction was executed relative to other executed instructions that correspond to an instruction type within a sequence of executed instructions, identify a first data packet corresponding to a first packet type and sequentially ordered, according to the order number, with respect to data packets of the first packet type within a data trace log, identify a second data packet corresponding to a second packet type and sequentially ordered, according to the order number, with respect to data packets of the second packet type within the data trace log, and map the identified first and second data packets to the instruction, wherein at least one of the first or second data packets was generated post-retirement of the instruction.

公开(公告)号：US10073719B2

公开(公告)日：2018-09-11

申请号：US15131099

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F9/52 ,  G06F11/34 ,  G06F11/36 ,  G06F9/38 ,  G06F9/46 ,  G06F9/30 ,  G06F11/14

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

公开(公告)号：US09612938B2

公开(公告)日：2017-04-04

申请号：US13895595

申请日：2013-05-16

Applicant: Intel Corporation

Inventor： Frank Binns ,  Matthew C. Merten ,  Mayank Bomb ,  Beeman C. Strong ,  Peter Lachner ,  Jason W. Brandt ,  Itamar Kazachinsky ,  Ofer Levy ,  Md A. Rahman

IPC: G06F7/38 ,  G06F3/00 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3636 ,  G06F11/3024 ,  G06F11/3055 ,  G06F11/3476 ,  G06F11/348 ,  G06F2201/865

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for providing status of a processing device with a periodic synchronization point in an instruction tracing system. For example, the method may include generating a boundary packet based on a unique byte pattern in a packet log. The boundary packet provides a starting point for packet decode. The method may also include generating a plurality of state packets based on status information of the processor. The plurality of state packets follows the boundary packet when outputted into the packet log.

公开(公告)号：US20160378636A1

公开(公告)日：2016-12-29

申请号：US14751759

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Beeman C. Strong ,  Jason W. Brandt ,  Peter Lachner ,  Andreas Kleen ,  James B. Crossland ,  Toby Opferman

IPC: G06F11/34 ,  G06F11/30

CPC classification number: G06F11/3466 ,  G06F11/3024 ,  G06F2201/865

Abstract: In an embodiment, a processor includes a core that is to include fetch logic to fetch instructions that include first instructions and a second instruction. The core also includes execution logic to execute the instructions. The execution logic is to retrieve an operand value that is one of an immediate value, a register value, and a memory value stored in a memory location, responsive to execution of the second instruction. The core also includes logic to output a packet that includes a representation of the operand value responsive to execution of the second instruction. The core also includes processor trace (PT) logic to generate a processor trace that includes a plurality of PT packets, where each PT packet correspond to an outcome of execution of a respective first instruction. The processor trace logic is further to include the packet within the processor trace. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括一个核心，其核心是包括提取逻辑，以提取包括第一指令和第二指令的指令。 核心还包括执行指令的执行逻辑。 执行逻辑是响应于第二指令的执行，检索作为立即值，寄存器值和存储在存储单元中的存储器值之一的操作数值。 核心还包括输出包括响应于执行第二指令的操作数值的表示的数据包的逻辑。 核心还包括处理器跟踪（PT）逻辑以产生包括多个PT分组的处理器跟踪，其中每个PT分组对应于相应的第一指令的执行结果。 处理器跟踪逻辑进一步将数据包包含在处理器跟踪内。 描述和要求保护其他实施例。

公开(公告)号：US20160232041A1

公开(公告)日：2016-08-11

申请号：US15131099

申请日：2016-04-18

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F9/52 ,  G06F11/14 ,  G06F9/38

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行单元和至少一个最后一个分支记录（LBR）寄存器，用于存储在程序执行期间所采取的分支的地址信息。 该寄存器还可以存储事务指示符以指示在事务存储器（TM）事务期间是否采取了分支。 该寄存器可以进一步存储中止指示符以指示分支是否由事务中止引起。 描述和要求保护其他实施例。

公开(公告)号：US09354878B2

公开(公告)日：2016-05-31

申请号：US13918147

申请日：2013-06-14

Applicant: Intel Corporation

Inventor： Ravi Rajwar ,  Peter Lachner ,  Laura A. Knauth ,  Konrad K. Lai

IPC: G06F9/30 ,  G06F11/34 ,  G06F11/36 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/528 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3808 ,  G06F9/3812 ,  G06F9/3834 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F11/1407 ,  G06F11/3476 ,  G06F11/3636

Abstract: In one embodiment, a processor includes an execution unit and at least one last branch record (LBR) register to store address information of a branch taken during program execution. This register may further store a transaction indicator to indicate whether the branch was taken during a transactional memory (TM) transaction. This register may further store an abort indicator to indicate whether the branch was caused by a transaction abort. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行单元和至少一个最后一个分支记录（LBR）寄存器，用于存储在程序执行期间所采取的分支的地址信息。 该寄存器还可以存储事务指示符以指示在事务存储器（TM）事务期间是否采取了分支。 该寄存器可以进一步存储中止指示符以指示分支是否由事务中止引起。 描述和要求保护其他实施例。

公开(公告)号：US11513940B2

公开(公告)日：2022-11-29

申请号：US17115967

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Rolf Kuehnis ,  Peter Lachner

IPC: G06F11/34 ,  G06F11/30 ,  G06F15/78

Abstract: In one embodiment, an apparatus includes: a first trace source to generate a plurality of first trace messages and a first local platform description identifier to identify the first trace source; a second trace source to generate a plurality of second trace messages and a second local platform description identifier to identify the second trace source; and a trace aggregator coupled to the first and the second trace sources, the trace aggregator to generate a global platform description identifier for the apparatus and output a trace stream including the global platform destination identifier, the first and second local platform description identifiers, the plurality of first trace messages and the plurality of second trace messages. Other embodiments are described and claimed.