公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20230317706A1

公开(公告)日：2023-10-05

申请号：US17710753

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Kuang LIU ,  Bohan SHAN ,  Hongxia FENG ,  Don Douglas JOSEPHSON ,  Stephen MOREIN ,  Kaladhar RADHAKRISHNAN

IPC: H01L25/18 ,  H01L23/373 ,  H01L25/065 ,  H01L23/00 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L25/18 ,  H01L23/3736 ,  H01L25/0652 ,  H01L24/40 ,  H01L23/538 ,  H01L21/4871 ,  H01L24/37 ,  H01L2224/37147 ,  H01L24/83 ,  H01L2224/83385 ,  H01L2224/83447 ,  H01L24/33 ,  H01L2224/3303 ,  H01L24/06 ,  H01L2224/0603 ,  H01L2224/32258 ,  H01L2224/4046 ,  H01L24/32 ,  H01L2224/40499 ,  H01L24/16 ,  H01L2224/16225

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a package substrate, and a die on the package substrate. In an embodiment, the electronic package further comprises a voltage regulator on the package substrate adjacent to the die, and a metal printed circuit board (PCB) heat spreader. In an embodiment, a trace on the metal PCB heat spreader couples the die to the voltage regulator.

公开(公告)号：US20230209759A1

公开(公告)日：2023-06-29

申请号：US18112953

申请日：2023-02-22

Applicant: Intel Corporation

Inventor： Karumbu MEYYAPPAN ,  Kyle ARRINGTON ,  David CRAIG ,  Pooya TADAYON

IPC: H05K7/14 ,  H05K7/20 ,  H01L23/22

CPC classification number: H05K7/1481 ,  H05K7/20272 ,  H01L23/22

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate having a first surface and a second surface opposite from the first surface, and a die on the first surface of the package substrate. In an embodiment, the electronic package further comprises a socket interface on the second surface of the package substrate. In an embodiment, the socket interface comprises a first layer, wherein the first layer comprises a plurality of wells, a liquid metal within the plurality of wells, and a second layer over the plurality of wells.

公开(公告)号：US20210272885A1

公开(公告)日：2021-09-02

申请号：US16803887

申请日：2020-02-27

Applicant: Intel Corporation

Inventor： Kyle ARRINGTON ,  Aaron MCCANN ,  Weston K. BERTRAND

IPC: H01L23/495 ,  H01L23/498 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate and an interposer over the package substrate. In an embodiment, the interposer comprises a ceramic. In an embodiment, the electronic package further comprises a first die over the interposer and a second die over the interposer. In an embodiment, the first die and the second die are electrically coupled together by the interposer. In an embodiment, the electronic package further comprises an integrated heat spreader (IHS) over the first die and the second die.

公开(公告)号：US20210195798A1

公开(公告)日：2021-06-24

申请号：US16723865

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Nicholas NEAL ,  Nicholas S. HAEHN ,  Je-Young CHANG ,  Kyle ARRINGTON ,  Aaron MCCANN ,  Edvin CETEGEN ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN ,  Ken P. HACKENBERG ,  Sergio A. CHAN ARGUEDAS

IPC: H05K7/20 ,  H01L23/367 ,  H01L23/00 ,  H01L23/498

Abstract: Embodiments include semiconductor packages. A semiconductor package includes dies on a package substrate, an integrated heat spreader (IHS) with a lid and sidewalls over the dies and package substrate, and a heatsink and a thermal interface material respectively on the IHS. The semiconductor package includes a vapor chamber defined by a surface of the package substrate and surfaces of the lid and sidewalls, and a wick layer in the vapor chamber. The wick layer is on the dies, package substrate, and IHS, where the vapor chamber has a vapor space defined by surfaces of the wick layer and lid of the IHS. The sidewalls are coupled to the package substrate with a sealant that hermetically seals the vapor chamber with the surfaces of the package substrate and the sidewalls and lid. The wick layer has a uniform or non-uniform thickness, and has porous materials including metals, powders, or graphite.