公开(公告)号：US20170103941A1

公开(公告)日：2017-04-13

申请号：US15028278

申请日：2015-05-13

Applicant: INTEL CORPORATION

Inventor： Zheng Zhou ,  Mihir K. Roy ,  Chong Zhang ,  Kyu-Oh Lee ,  Amanda E. Schuckman

IPC: H01L23/498 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/14 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

公开(公告)号：US11901115B2

公开(公告)日：2024-02-13

申请号：US17873509

申请日：2022-07-26

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Rahul Jain ,  Sai Vadlamani ,  Cheng Xu ,  Ji Yong Park ,  Junnan Zhao ,  Seo Young Kim

IPC: H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01F27/327 ,  H01F27/2804 ,  H01F41/043 ,  H01L21/486 ,  H01L21/4857 ,  H01L21/4867 ,  H01L23/49822 ,  H01L23/49838 ,  H01F2027/2809 ,  H01L21/6835 ,  H01L24/16 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16267 ,  H01L2924/19042 ,  H01L2924/19102

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US11581271B2

公开(公告)日：2023-02-14

申请号：US16353164

申请日：2019-03-14

Applicant: Intel Corporation

Inventor： Rahul Jain ,  Kyu-Oh Lee ,  Islam A. Salama ,  Amruthavalli P. Alur ,  Wei-Lun K. Jen ,  Yongki Min ,  Sheng C. Li

IPC: H01L23/64 ,  H01L23/498 ,  H01L49/02 ,  H01L23/538

Abstract: Embodiments include semiconductor packages. A semiconductor package includes a plurality of build-up layers and a plurality of conductive layers in the build-up layers. The conductive layers include a first conductive layer and a second conductive layer. The first conductive layer is over the second conductive layer and build-up layers, where a first via couples the first and second conductive layers. The semiconductor package also includes a thin film capacitor (TFC) in the build-up layers, where a second via couples the TFC to the first conductive layer, and the second via has a thickness less than a thickness of the first via. The first conductive layer may be first level interconnects. The build-up layers may be dielectrics. The TFC may include a first electrode, a second electrode, and a dielectric. The first electrode may be over the second electrode, and the dielectric may be between the first and second electrodes.

公开(公告)号：US11450471B2

公开(公告)日：2022-09-20

申请号：US15938119

申请日：2018-03-28

Applicant: Intel Corporation

Inventor： Cheng Xu ,  Kyu-Oh Lee ,  Junnan Zhao ,  Rahul Jain ,  Ji Yong Park ,  Sai Vadlamani ,  Seo Young Kim

IPC: H01F27/24 ,  H01F27/28 ,  H01F27/02

Abstract: Embodiments include an inductor that comprises an inductor trace and a magnetic body surrounding the inductor trace. In an embodiment, the magnetic body comprises a first step surface and a second step surface. Additional embodiments include an inductor that includes a barrier layer. In an embodiment, an inductor trace is formed over a first surface of the barrier layer. Embodiments include a first magnetic body over the inductor trace and the first surface of the barrier layer, and a second magnetic body over a second surface of the barrier layer opposite the first surface. In an embodiment, a width of the second magnetic body is greater than a width of the first magnetic body.

公开(公告)号：US11443892B2

公开(公告)日：2022-09-13

申请号：US16020035

申请日：2018-06-27

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Rahul Jain ,  Sai Vadlamani ,  Cheng Xu ,  Ji Yong Park ,  Junnan Zhao ,  Seo Young Kim

IPC: H01L27/32 ,  H01F27/32 ,  H01L23/498 ,  H01F41/04 ,  H01L21/48 ,  H01F27/28 ,  H01L21/683 ,  H01L23/00

Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.

公开(公告)号：US10446500B2

公开(公告)日：2019-10-15

申请号：US16184726

申请日：2018-11-08

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H05K3/46 ,  H01L25/065

Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.

公开(公告)号：US09917044B2

公开(公告)日：2018-03-13

申请号：US15028278

申请日：2015-05-13

Applicant: INTEL CORPORATION

Inventor： Zheng Zhou ,  Mihir K. Roy ,  Chong Zhang ,  Kyu-Oh Lee ,  Amanda E. Schuckman

IPC: H01L23/52 ,  H01L23/498 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76804 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49838 ,  H01L23/66 ,  H01L24/14 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311

Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

公开(公告)号：US09865568B2

公开(公告)日：2018-01-09

申请号：US15038008

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Kyu-Oh Lee ,  Islam A. Salama ,  Ram S. Viswanath ,  Robert L. Sankman ,  Babak Sabi ,  Sri Chaitra Jyotsna Chavali

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/48 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/11 ,  H01L24/17 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/16225 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/15311

Abstract: Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may include: an IC package having a first resist surface; a recess disposed in the first resist surface, wherein a bottom of the recess includes a second resist surface; a first plurality of conductive contacts located at the first resist surface; and a second plurality of conductive contacts located at the second resist surface. Other embodiments may be disclosed and/or claimed.