公开(公告)号：US20220229661A1

公开(公告)日：2022-07-21

申请号：US17712966

申请日：2022-04-04

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Jonathan D. PEARCE ,  Guei-Yuan LUEH ,  ElMoustapha OULD-AHMED-VALL ,  Jorge E. PARRA ,  Prasoonkumar SURTI ,  Krishna N. VINOD ,  Ronen ZOHAR

IPC: G06F9/30

Abstract: Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

公开(公告)号：US20210082154A1

公开(公告)日：2021-03-18

申请号：US17003040

申请日：2020-08-26

Applicant: INTEL CORPORATION

Inventor： Carson BROWNLEE ,  Carsten BENTHIN ,  Joshua BARCZAK ,  Kai XIAO ,  Michael APODACA ,  Prasoonkumar SURTI ,  Thomas RAOUX

IPC: G06T9/40 ,  G06T15/06 ,  G06T15/20 ,  G06T1/60

Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

公开(公告)号：US20210049808A1

公开(公告)日：2021-02-18

申请号：US17003011

申请日：2020-08-26

Applicant: INTEL CORPORATION

Inventor： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC: G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20200265636A1

公开(公告)日：2020-08-20

申请号：US16802400

申请日：2020-02-26

Applicant: INTEL CORPORATION

Inventor： Brent E. INSKO ,  Prasoonkumar SURTI

IPC: G06T15/40 ,  G06T15/00 ,  H04N13/279

Abstract: An apparatus and method are described for performing an early depth test on graphics data. For example, one embodiment of a graphics processing apparatus comprises: early depth test circuitry to perform an early depth test on blocks of pixels to determine whether all pixels in the block of pixels can be resolved by the early depth test; a plurality of execution circuits to execute pixel shading operations on the blocks of pixels; and a scheduler circuit to schedule the blocks of pixels for the pixel shading operations, the scheduler circuit to prioritize the blocks of pixels in accordance with the determination as to whether all pixels in the block of pixels can be resolved by the early depth test.

公开(公告)号：US20160189338A1

公开(公告)日：2016-06-30

申请号：US15060317

申请日：2016-03-03

Applicant: INTEL CORPORATION

Inventor： Tomas G. AKENINE-MOLLER ,  Jim K. NILSSON ,  Prasoonkumar SURTI ,  Jon N. HASSELGREN ,  Carl J. MUNKBERG

IPC: G06T1/60 ,  G06T7/40 ,  G06K9/46 ,  G06T11/00

CPC classification number: G06T1/60 ,  G06K9/4652 ,  G06K2009/4666 ,  G06T7/90 ,  G06T9/00 ,  G06T11/00 ,  G06T2200/28 ,  G06T2207/20021

Abstract: Techniques related to graphics rendering including techniques for compression and/or decompression of graphics data by use of pixel region bit values are described.

Abstract translation: 描述了与图形渲染相关的技术，包括通过使用像素区域位值来压缩和/或解压缩图形数据的技术。

公开(公告)号：US20240233244A1

公开(公告)日：2024-07-11

申请号：US18413286

申请日：2024-01-16

Applicant: INTEL CORPORATION

Inventor： Scott JANUS ,  Prasoonkumar SURTI ,  Karthik VAIDYANATHAN ,  Alexey SUPIKOV ,  Gabor LIKTOR ,  Carsten BENTHIN ,  Philip LAWS ,  Michael DOYLE

IPC: G06T15/06 ,  G06T1/60 ,  G06T15/00 ,  G06T17/00

CPC classification number: G06T15/06 ,  G06T1/60 ,  G06T15/005 ,  G06T17/005 ,  G06T2210/21

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20240184739A1

公开(公告)日：2024-06-06

申请号：US18432859

申请日：2024-02-05

Applicant: INTEL CORPORATION

Inventor： Joydeep RAY ,  Niranjan COORAY ,  Subramaniam MAIYURAN ,  Altug KOKER ,  Prasoonkumar SURTI ,  Varghese GEORGE ,  Valentin ANDREI ,  Abhishek APPU ,  Guadalupe GARCIA ,  Pattabhiraman K ,  Sungye KIM ,  Sanjay KUMAR ,  Pratik MAROLIA ,  Elmoustapha OULD-AHMED-VALL ,  Vasanth RANGANATHAN ,  William SADLER ,  Lakshminarayanan STRIRAMASSARMA

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/06 ,  H03M7/46

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：US20230418617A1

公开(公告)日：2023-12-28

申请号：US18339454

申请日：2023-06-22

Applicant: INTEL CORPORATION

Inventor： Christopher J. HUGHES ,  Prasoonkumar SURTI ,  Guei-Yuan LUEH ,  Adam T. LAKE ,  Jill BOYCE ,  Subramaniam MAIYURAN ,  Lidong XU ,  James M. HOLLAND ,  Vasanth RANGANATHAN ,  Nikos KABURLASOS ,  Altug KOKER ,  Abhishek R. Appu

IPC: G06F9/38 ,  G06F12/084 ,  G06T1/60 ,  G06F9/50 ,  G06F9/54

CPC classification number: G06F9/3891 ,  G06F12/084 ,  G06T1/60 ,  G06F9/5066 ,  G06F9/544

Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive data dependencies for one or more tasks comprising one or more producer tasks executing on the first processing resource and one or more consumer tasks executing on the second processing resource and move a data output from one or more producer tasks executing on the first processing resource to a cache memory communicatively coupled to the second processing resource. Other embodiments may be described and claimed.

公开(公告)号：US20230297513A1

公开(公告)日：2023-09-21

申请号：US17699062

申请日：2022-03-18

Applicant: Intel Corporation

Inventor： Prasoonkumar SURTI ,  Tobias ZIRR ,  Abhishek R. APPU ,  Anton KAPLANYAN ,  Pawel MAJEWSKI ,  Joshua BARCZAK

IPC: G06F12/0897 ,  G06N20/00

CPC classification number: G06F12/0897 ,  G06N20/00 ,  G06F2212/60

Abstract: A cache streaming apparatus and method for machine learning. For example, one embodiment of an apparatus comprises: a plurality of compute units to perform machine learning operations; a cache subsystem comprising a hierarchy of cache levels, at least some of the cache levels shared by two or more of the plurality of compute units; and data streaming hardware logic to stream machine learning data in and out of the cache subsystem based on the machine learning operations, the data streaming hardware logic to load data into the cache subsystem from memory before the data is needed by a first portion of the machine learning operations and to ensure that results produced by the first portion of machine learning operations are maintained in the cache subsystem until used by a second portion of the machine learning operations.

公开(公告)号：US20230206383A1

公开(公告)日：2023-06-29

申请号：US17561666

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： Karol A. SZERSZEN ,  Prasoonkumar SURTI ,  Vidhya KRISHNAN ,  Aditya NAVALE ,  Abhishek R. APPU ,  Altug KOKER ,  Ronald W. SILVAS

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/084

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06F12/084 ,  G06F2212/401

Abstract: A system includes a compression engine that stores the compression format information embedded in the compressed data. The compression format information can be included in a header that includes compression control surface (CCS) information. The system includes a shared memory to store compressed data for multiple hardware pipelines, where blocks of the compressed data have a common memory footprint and the compression header. The compression engine can compress data to store in the shared memory including generation of the header. The compression engine can decompress data read from the shared memory, including identification of the compression format from the header.