公开(公告)号：US20210014133A1

公开(公告)日：2021-01-14

申请号：US17032993

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Christian Maciocco ,  Kshitij Doshi ,  Francesc Guim Bernat ,  Ned M. Smith ,  Marcin Spoczynski ,  Timothy Verrall ,  Rajesh Gadiyar ,  Trevor Cooper ,  Valerie Parker

IPC: H04L12/24 ,  H04L12/26 ,  H04L29/08

Abstract: Methods and apparatus to coordinate edge platforms are disclosed. A disclosed example apparatus includes to control processing of data associated with edges includes an orchestrator analyzer to determine a first performance requirement of a first microservice of an application and a second performance requirement of a second microservice of the application. The apparatus also includes an orchestrator controller to assign the first microservice and the second microservice across first and second edge nodes between a source network and a destination network by: assigning the first microservice to the first edge node based on a first capability of the first edge node satisfying the first performance requirement of the first microservice, and assigning the second microservice to the second edge node based on a second capability of the second edge node satisfying the second performance requirement of the second microservice.

公开(公告)号：US20230205606A1

公开(公告)日：2023-06-29

申请号：US17922277

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Neelam Chandwani ,  Kshitij Doshi ,  Chetan Hiremath ,  Rajesh Gadiyar ,  Udayan Mukherjee ,  Daniel Towner ,  Valerie Parker ,  Shubha Bommalingaiahnapallya ,  Rany ElSayed

IPC: G06F9/50

CPC classification number: G06F9/5094 ,  G06F9/505 ,  G06F9/5044

Abstract: Systems, apparatus, and methods to workload optimize hardware are disclosed herein. An example apparatus includes power control circuitry to determine an application ratio based on an instruction to be executed by one or more cores of a processor to execute a workload, and configure, before the execution of the workload, at least one of (i) the one or more cores of the processor based on the application ratio or (ii) uncore logic of the processor based on the application ratio, and execution circuitry to execute the workload with the at least one of the one or more cores or the uncore logic.

公开(公告)号：US11539596B2

公开(公告)日：2022-12-27

申请号：US17494511

申请日：2021-10-05

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Ned M. Smith ,  Francesc Guim Bernat ,  Timothy Verrall ,  Rajesh Gadiyar

IPC: H04L41/142 ,  H04L41/16 ,  H04L41/0816 ,  H04L67/10

Abstract: Systems and techniques for end-to-end quality of service in edge computing environments are described herein. A set of telemetry measurements may be obtained for an ongoing dataflow between a device and a node of an edge computing system. A current key performance indicator (KPI) may be calculated for the ongoing dataflow. The current KPI may be compared to a target KPI to determine an urgency value. A set of resource quality metrics may be collected for resources of the network. The set of resource quality metrics may be evaluated with a resource adjustment model to determine available resource adjustments. A resource adjustment may be selected from the available resource adjustments based on an expected minimization of the urgency value. Delivery of the ongoing dataflow may be modified using the selected resource adjustment.

公开(公告)号：US20220197685A1

公开(公告)日：2022-06-23

申请号：US17392861

申请日：2021-08-03

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Gerald Rogers ,  Shih-Wei Roger Chien ,  Namakkal Venkatesan ,  Rajesh Gadiyar

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/50 ,  G06F9/38

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

公开(公告)号：US11146455B2

公开(公告)日：2021-10-12

申请号：US16722740

申请日：2019-12-20

Applicant: Intel Corporation

Inventor： Kshitij Arun Doshi ,  Ned M. Smith ,  Francesc Guim Bernat ,  Timothy Verrall ,  Rajesh Gadiyar

IPC: H04L12/24 ,  H04L29/08

Abstract: Systems and techniques for end-to-end quality of service in edge computing environments are described herein. A set of telemetry measurements may be obtained for an ongoing dataflow between a device and a node of an edge computing system. A current key performance indicator (KPI) may be calculated for the ongoing dataflow. The current KPI may be compared to a target KPI to determine an urgency value. A set of resource quality metrics may be collected for resources of the network. The set of resource quality metrics may be evaluated with a resource adjustment model to determine available resource adjustments. A resource adjustment may be selected from the available resource adjustments based on an expected minimization of the urgency value. Delivery of the ongoing dataflow may be modified using the selected resource adjustment.

公开(公告)号：US11086650B2

公开(公告)日：2021-08-10

申请号：US15904371

申请日：2018-02-25

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Gerald Rogers ,  Shih-Wei Roger Chien ,  Namakkal Venkatesan ,  Rajesh Gadiyar

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0811 ,  G06F9/50 ,  G06F9/38

Abstract: Technologies for application-specific network acceleration include a computing device including a processor and an accelerator device such as a field-programmable gate array (FPGA). The processor and the accelerator device are coupled via a coherent interconnect and may be included in a multi-chip package. The computing device binds a virtual machine executed by the processor with an application function unit of the accelerator device via the coherent interconnect. The computing device processes network application data with the virtual machine and the application function unit within a coherency domain maintained with the coherent interconnect. Processing the network data may include processing a packet of a network flow by the virtual machine and processing subsequent packets of the network flow by the application function unit. Other embodiments are described and claimed.

公开(公告)号：US12278690B2

公开(公告)日：2025-04-15

申请号：US17849402

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Valerie J. Parker ,  Udayan Mukherjee ,  Rajesh Gadiyar ,  Jason K. Smith

IPC: H04B7/185

Abstract: Various approaches for the deployment and coordination of inter-satellite communication pathways, defined for use with a satellite non-terrestrial network, are discussed. Among other examples, such inter-satellite communication pathways may be identified, reserved, allocated, and used for ultra-low-latency communication purposes.

公开(公告)号：US20250071662A1

公开(公告)日：2025-02-27

申请号：US18824399

申请日：2024-09-04

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Chetan Hiremath ,  Rajesh Gadiyar ,  Jason K. Smith ,  Valerie J. Parker ,  Udayan Mukherjee ,  Neelam Chandwani ,  Francesc Guim Bernat ,  Ned M. Smith

IPC: H04W48/02 ,  H04B7/185 ,  H04B7/195 ,  H04W16/28 ,  H04W84/06

Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

公开(公告)号：US20230217253A1

公开(公告)日：2023-07-06

申请号：US17922280

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Stephen Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Rany ElSayed ,  Lokpraveen Mosur ,  Neelam Chandwani ,  Pinkesh Shah ,  Rajesh Gadiyar ,  Shrikant M. Shah ,  Uzair Qureshi

IPC: H04W12/125 ,  G06F9/50

CPC classification number: H04W12/125 ,  G06F9/505

Abstract: Systems, methods, and apparatus for workload optimized central processing units are disclosed herein. An example apparatus includes a workload analyzer to determine an application ratio associated with the workload, the application ratio based on an operating frequency to execute the workload, a hardware configurator to configure, before execution of the workload, at least one of (i) one or more cores of the processor circuitry based on the application ratio or (ii) uncore logic of the processor circuitry based on the application ratio, and a hardware controller to initiate the execution of the workload with the at least one of the one or more cores or the uncore logic.

公开(公告)号：US20220255916A1

公开(公告)日：2022-08-11

申请号：US17628896

申请日：2020-09-30

Applicant: INTEL CORPORATION

Inventor： Ned M. Smith ,  Dario Sabella ,  Kshitij Arun Doshi ,  Francesc Guim Bernat ,  Rajesh Gadiyar

IPC: H04L9/40

Abstract: Methods and apparatus to attest objects in edge computing environments are disclosed. An example apparatus generate an attestation information object in an edge computing environment includes an evidence collector to collect evidence for an attestation information object to attest the authenticity of a first object, a temporal data generator to generate temporal information associated with data associated with the object, the evidence collector to associate the evidence and the temporal information with the first object, and an interface generator to generate an interface for the attestation information object.