公开(公告)号：US20240321737A1

公开(公告)日：2024-09-26

申请号：US18125440

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Charles H. Wallace ,  Shengsi Liu ,  Saurabh Acharya

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/5283 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778

Abstract: Techniques are provided herein to form semiconductor devices having one or more source or drain regions with backside contacts that are separated using dielectric walls. In an example, a first semiconductor device includes a first semiconductor region, such as one or more first nanoribbons, extending from a first source or drain region, and a second semiconductor device including a second semiconductor region, such as one or more second nanoribbons, extending from a second source or drain region adjacent to the first source or drain region. A first conductive contact abuts the underside of the first source or drain region and a second conductive contact abuts the underside of the second source or drain region. A dielectric wall extends between the first and second contacts, thus separating them from contacting each other. The dielectric wall also extends between the first source or drain region and the second source or drain region.

公开(公告)号：US20240321685A1

公开(公告)日：2024-09-26

申请号：US18125430

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Baofu Zhu ,  Charles H. Wallace

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/823481 ,  H01L27/088

Abstract: Techniques are provided herein to form semiconductor devices arranged between a gate cut on one side and a deep backside via on the other side. A row of semiconductor devices each include a semiconductor region extending in a first direction between corresponding source or drain regions, and a gate structure extending in a second direction over the semiconductor regions. Each semiconductor device may be separated from an adjacent semiconductor device along the second direction by either a gate cut or a deep backside via. The gate cut may be a dielectric wall that extends through an entire thickness of the gate structure and the deep backside via may include a conductive layer and a dielectric barrier that also extend through at least an entire thickness of the gate structure. Each semiconductor device may include a gate cut on one side and a deep backside via on the other side.

公开(公告)号：US20230282701A1

公开(公告)日：2023-09-07

申请号：US17687045

申请日：2022-03-04

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Robert Joachim ,  Mohammad Hasan ,  Tahir Ghani

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696 ,  H01L27/0886

Abstract: Techniques are provided herein to form semiconductor devices having gate cut structures. Adjacent semiconductor devices having semiconductor regions (e.g., fins or nanoribbons) extending in a first direction have a gate structure that extends over the semiconductor regions in a second direction and are separated by a gate cut structure extending in the first direction and interrupting the gate structure. The gate cut structure further extends between adjacent source or drain regions (corresponding to the adjacent semiconductor devices). A dielectric liner on at least a sidewall and/or top surface of the source or drain regions and also extends up a sidewall surface of the gate cut structure. In some cases, the gate structure includes a gate dielectric present on the semiconductor regions, but not present on the gate cut structure. A contact may pass through the liner and at least partially land on a source or drain region.