公开(公告)号：US20230275085A1

公开(公告)日：2023-08-31

申请号：US17682037

申请日：2022-02-28

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Sukru Yemenicioglu ,  Mohit K. Haran ,  Shengsi Liu ,  Robert Joachim ,  Dan S. Lavric ,  Stephen M. Cea

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L27/088 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78696 ,  H01L29/41775

Abstract: Techniques are provided herein to form an integrated circuit having a grid of gate cut structures such that a gate cut structure exists between pairs of semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. Each of the gate cut structures may be formed at the same time in a grid-like pattern across the integrated circuit (or a portion thereof). Sidewall spacer structures on the sidewalls of the gate structure wrap around ends of each gate structure to form a given gate cut structure.

公开(公告)号：US20240429276A1

公开(公告)日：2024-12-26

申请号：US18212295

申请日：2023-06-21

Applicant: Intel Corporation

Inventor： Sukru Yemenicioglu ,  Leonard P. Guler ,  Shengsi Liu

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Techniques are provided herein to form semiconductor devices having cells that include forksheet devices with source or drain regions of the same dopant type on both sides of the forksheet dielectric spine. The techniques can be used in any number of integrated circuit applications and are particularly useful with respect to logic and memory cells. The forksheet devices may include all p-type source or drain regions on both sides of the dielectric spine or all n-type source or drain regions on both sides of the dielectric spine. Using forksheet devices with the same dopant type allows for both forksheet transistors and gate-all-around (GAA) transistors to be included within the same cell. The cell boundaries may also be placed along the forksheet dielectric spines rather than along gate cuts, which provides greater flexibility when designing multi-height cells.

公开(公告)号：US20240321738A1

公开(公告)日：2024-09-26

申请号：US18125455

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Prabhjot Kaur Luthra ,  Nidhi Khandelwal ,  Marie T. Conte ,  Saurabh Acharya ,  Shengsi Liu ,  Gary Allen ,  Clifford J. Engel ,  Charles H. Wallace

IPC: H01L23/528 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L23/5283 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/778

Abstract: Techniques to form an integrated circuit having a bridging contact structure. A bridging contact structure may, for example, bridge between source/drain contacts and to an adjacent gate electrode within the same device layer. In an example, a gate cut structure extends in a first direction to separate the source or drain regions and gate structures of neighboring semiconductor devices. Contacts may be formed over the source or drain regions of the neighboring devices on opposite sides of the gate cut along a second direction orthogonal to the first direction. A portion of the gate cut is replaced with a first conductive bridge between the source or drain contacts. A portion of one or more dielectric barriers between one of the source or drain contacts and an adjacent gate electrode is replaced with a second conductive bridge in the first direction between the source or drain contact and the gate structure.

公开(公告)号：US20240241446A1

公开(公告)日：2024-07-18

申请号：US18620262

申请日：2024-03-28

Applicant: Intel Corporation

Inventor： Marvin Paik ,  Charles H. Wallace ,  Leonard Guler ,  Elliot N. Tan ,  Shengsi Liu ,  Vivek Vishwakarma ,  Izabela Samek ,  Mohammadreza Soleymaniha

IPC: G03F7/20 ,  G03F7/00 ,  H01L21/027

CPC classification number: G03F7/2022 ,  G03F7/2004 ,  G03F7/201 ,  G03F7/70033 ,  G03F7/7005 ,  G03F7/70525 ,  G03F7/7055 ,  G03F7/70725 ,  H01L21/0275

Abstract: Apparatus and methods are disclosed. An example lithography apparatus includes an ultraviolet (UV) source to expose a photoresist layer to UV light; and an extreme ultraviolet (EUV) source coupled to the UV source, the EUV source to expose the photoresist layer to EUV light to via a photomask, a combination of the UV light and the EUV light provide a pattern on the photoresist layer when a developer solution is applied to the photoresist layer.

公开(公告)号：US20240355891A1

公开(公告)日：2024-10-24

申请号：US18753781

申请日：2024-06-25

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Baofu Zhu ,  Meenakshisundaram Ramanathan ,  Charles H. Wallace ,  Ankit Kirit Lakhani

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

公开(公告)号：US20240355890A1

公开(公告)日：2024-10-24

申请号：US18136991

申请日：2023-04-20

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Baofu Zhu ,  Meenakshisundaram Ramanathan ,  Charles H. Wallace ,  Ankit Kirit Lakhani

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.

公开(公告)号：US20240321978A1

公开(公告)日：2024-09-26

申请号：US18125456

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Baofu Zhu ,  Charles H. Wallace ,  Clifford J. Engel ,  Gary Allen ,  Saurabh Acharya ,  Thomas Obrien

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: Techniques are provided herein to form semiconductor devices that include a contact over a given source or drain region that extends over the top of an adjacent source or drain region without contacting it. In an example, a semiconductor device includes a gate structure around a fin of semiconductor material that extends from a source or drain region, or one or more nanowires or nanoribbons or nanosheets of semiconductor material that extend from the source or drain region. A conductive contact is formed over the source or drain region that extends laterally across the source/drain trench above an adjacent source or drain region without contacting the adjacent source or drain region. The contact may extend along the source/drain trench through a dielectric wall (e.g., a gate cut) that extends orthogonally through the source/drain trench.

公开(公告)号：US20220413376A1

公开(公告)日：2022-12-29

申请号：US17358446

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Leonard Guler ,  Tahir Ghani ,  Charles Wallace ,  Hossam Abdallah ,  Dario Farias ,  Tsuan-Chung Chang ,  Chia-Ho Tsai ,  Chetana Singh ,  Desalegne Teweldebrhan ,  Robert Joachim ,  Shengsi Liu

IPC: G03F1/22 ,  G03F7/20 ,  H01L21/033 ,  H01L21/311

Abstract: Techniques for improved extreme ultraviolet (EUV) patterning using assist features, related transistor structures, integrated circuits, and systems, are disclosed. A number of semiconductor fins and assist features are patterned into a semiconductor substrate using EUV. The assist features increase coverage of absorber material in the EUV mask, thereby reducing bright field defects in the EUV patterning. The semiconductor fins and assist features are buried in fill material and a mask is patterned that exposes the assist features and covers the semiconductor fins. The exposed assist features are partially removed and the protected active fins are ultimately used in transistor devices.

公开(公告)号：US20250072069A1

公开(公告)日：2025-02-27

申请号：US18455446

申请日：2023-08-24

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Desalegne B. Teweldebrhan ,  Shengsi Liu ,  Saurabh Acharya ,  Marko Radosavljevic ,  Richard Schenker

IPC: H01L29/08 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06

Abstract: Techniques to form semiconductor device conductive interconnections. In an example, an integrated circuit includes a recessed via and a conductive bridge between a top surface of the recessed via and an adjacent source or drain contact. A transistor device includes a semiconductor material extending from a source or drain region, a gate structure over the semiconductor material, and a contact on the source or drain region. Adjacent to the source or drain region, a deep via structure extends in a vertical direction through an entire thickness of the gate structure. The via structure includes a conductive via that is recessed below a top surface of the conductive contact. A conductive bridge extends between the contact and the conductive via such that the conductive bridge contacts a portion of the contact and at least a portion of a top surface of the conductive via.

公开(公告)号：US20240321872A1

公开(公告)日：2024-09-26

申请号：US18125447

申请日：2023-03-23

Applicant: Intel Corporation

Inventor： Leonard P. Guler ,  Shengsi Liu ,  Saurabh Acharya ,  Thomas Obrien ,  Krishna Ganesan ,  Ankit Kirit Lakhani ,  Prabhjot Kaur Luthra ,  Nidhi Khandelwal ,  Clifford J. Engel ,  Baofu Zhu ,  Meenakshisundaram Ramanathan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/778 ,  H01L29/786

CPC classification number: H01L27/088 ,  H01L21/823437 ,  H01L21/823475 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/778 ,  H01L29/78696

Abstract: Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.