公开(公告)号：US20210407903A1

公开(公告)日：2021-12-30

申请号：US16914062

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Georgios Dogiamis ,  Henning Braunisch ,  Beomseok Choi ,  William J. Lambert ,  Stephen Morein ,  Ahmed Abou-Alfotouh ,  Johanna Swan

IPC: H01L23/522 ,  H01L23/532 ,  H05K1/11 ,  H05K3/14 ,  H01L21/768

Abstract: An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.

公开(公告)号：US20210407888A1

公开(公告)日：2021-12-30

申请号：US16914066

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Stephen Morein ,  Feras Eid ,  Georgios Dogiamis

IPC: H01L23/467 ,  B01F13/00 ,  C23C24/04 ,  H01L23/473

Abstract: A microfluidic device having a channel within a first material to thermally couple with an IC die. The channel defines an initial fluid path between a fluid inlet port and a fluid outlet port. A second material is within a portion of the channel. The second material supplements the first material to modify the initial fluid path into a final fluid path between the fluid inlet port and the fluid outlet port. The second material may have a different composition and/or microstructure than the first material.

公开(公告)号：US12243828B2

公开(公告)日：2025-03-04

申请号：US17355770

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18 ,  H05K1/18

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

公开(公告)号：US20250062278A1

公开(公告)日：2025-02-20

申请号：US18452152

申请日：2023-08-18

Applicant: Intel Corporation

Inventor： Sagar Suthram ,  Debendra Mallik ,  Wilfred Gomes ,  Pushkar Sharad Ranade ,  Nitin A. Deshpande ,  Ravindranath Vithal Mahajan ,  Abhishek A. Sharma ,  Joshua Fryman ,  Stephen Morein ,  Matthew Adiletta ,  Michael Crocker ,  Aaron Gorius

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522

Abstract: Embodiments of a microelectronic assembly may include a first integrated circuit (IC) die having a first surface, a second surface opposite the first surface, and a third surface orthogonal to the first and second surfaces, the first IC die including a conductive trace that is parallel to the first and second surfaces, and the conductive trace is exposed at the third surface; and a second IC die including a fourth surface, wherein the fourth surface of the second IC die is electrically coupled to the third surface of the first IC die by an interconnect including solder.

公开(公告)号：US20240006381A1

公开(公告)日：2024-01-04

申请号：US17854728

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Stephen Morein ,  Ravindranath Vithal Mahajan ,  Prashant Majhi

IPC: H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06548

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of vertically stacked dies; a trench of dielectric material through the plurality of vertically stacked dies; and a plurality of conductive vias extending through the trench of dielectric material, wherein individual ones of the plurality of conductive vias are electrically coupled to individual ones of the plurality of vertically stacked dies.

公开(公告)号：US20240006366A1

公开(公告)日：2024-01-04

申请号：US17854613

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Stephen Morein ,  Ravindranath Vithal Mahajan ,  Prashant Majhi

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/24 ,  H01L2224/2405 ,  H01L24/20 ,  H01L2924/37001 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H01L2924/1431 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2924/15331 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/215 ,  H01L2224/24145 ,  H01L2224/24011 ,  H01L25/0652

Abstract: Disclosed herein are microelectronic assemblies, as well as related apparatuses and methods. In some embodiments, a microelectronic assembly may include a plurality of dies stacked vertically; a trench of dielectric material extending through the plurality of dies; a conductive via extending through the trench of dielectric material; and a plurality of conductive pathways between the plurality of dies and the conductive via, wherein individual ones of the conductive pathways are electrically coupled to the conductive via and to individual ones of the plurality of dies, and wherein the individual ones of the plurality of conductive pathways have a first portion including a first material and a second portion including a second material different from the first material.

公开(公告)号：US20230099827A1

公开(公告)日：2023-03-30

申请号：US17484281

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Aleksandar Aleksov ,  Feras Eid ,  Wenhao Li ,  Stephen Morein ,  Yoshihiro Tomita

IPC: H01L23/532 ,  H01L21/768

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20230095654A1

公开(公告)日：2023-03-30

申请号：US17484213

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Stephen Morein ,  Krishna Bharath ,  Henning Braunisch ,  Beomseok Choi ,  Brandon M. Rawlings ,  Thomas L. Sounart ,  Johanna Swan ,  Yoshihiro Tomita ,  Aleksandar Aleksov

IPC: H01L23/498 ,  H01L23/48 ,  H01L25/065 ,  H01L21/48

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

公开(公告)号：US20220415815A1

公开(公告)日：2022-12-29

申请号：US17355770

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/48 ,  H01L23/00 ,  H01L25/16 ,  H05K1/18 ,  H01L25/065 ,  H01L25/18 ,  H01L23/367 ,  H01L25/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

公开(公告)号：US20250132259A1

公开(公告)日：2025-04-24

申请号：US18989232

申请日：2024-12-20

Applicant: Intel Corporation

Inventor： Bernd Waidhas ,  Carlton Hanna ,  Stephen Morein ,  Lizabeth Keser ,  Georg Seidemann

IPC: H01L23/538 ,  H01L23/50 ,  H01L23/522

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate, having a surface, including a first conductive pathway electrically coupled to a power source; a first microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by an insulating material; a second microelectronic component, having an active side electrically coupled to the surface of the package substrate and an opposing back side, surrounded by the insulating material and including a through-substrate via (TSV) electrically coupled to the first conductive pathway; and a redistribution layer (RDL), on the insulating material, including a second conductive pathway electrically coupling the TSV, the second surface of the second microelectronic component, and the second surface of the first microelectronic component.